📄 yunsuan22.rpt
字号:
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\computer\alu\yunsuan22.rpt
yunsuan22
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A4 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 12/22( 54%)
A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A12 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
A13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
A14 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 13/22( 59%)
A15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
A16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A17 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%)
A18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
A19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A20 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
A21 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
A22 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 15/22( 68%)
A23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
A24 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
B2 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C2 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C4 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 18/22( 81%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
C12 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 5/22( 22%)
C13 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
C14 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 13/22( 59%)
C16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 10/22( 45%)
C17 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
C18 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 19/22( 86%)
C19 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 9/22( 40%)
C20 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 9/22( 40%)
C21 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
C22 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
C23 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C24 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
C25 8/8 (100%) 3/8 ( 37%) 5/8 ( 62%) 1/2 2/2 17/22( 77%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 55/96 ( 57%)
Total logic cells used: 222/576 ( 38%)
Total embedded cells used: 8/24 ( 33%)
Total EABs used: 1/3 ( 33%)
Average fan-in: 2.90/4 ( 72%)
Total fan-in: 645/2304 ( 27%)
Total input pins required: 37
Total input I/O cell registers required: 0
Total output pins required: 24
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 222
Total flipflops required: 64
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 47/ 576 ( 8%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 8 1 7 1 0 0 0 1 1 0 7 0 8 7 8 8 7 8 8 8 6 8 8 8 118/0
B: 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2/0
C: 0 3 0 6 0 0 8 0 1 0 8 7 8 3 6 0 8 5 8 8 7 6 7 3 8 102/8
Total: 0 13 1 13 1 0 8 0 2 1 8 14 8 11 13 8 16 12 16 16 15 12 15 11 16 222/8
Device-Specific Information: d:\computer\alu\yunsuan22.rpt
yunsuan22
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
36 - - - 24 INPUT 0 0 0 8 ALU-BUS
55 - - - -- INPUT G 0 0 0 0 CLK-CDU
98 - - A -- INPUT 0 0 0 2 CN
91 - - B -- INPUT 0 0 0 1 DAT0
17 - - B -- INPUT 0 0 0 1 DAT1
22 - - B -- INPUT 0 0 0 1 DAT2
86 - - B -- INPUT 0 0 0 1 DAT3
118 - - - 07 INPUT 0 0 0 1 LDAR
95 - - A -- INPUT 0 0 0 1 LDDR1
99 - - A -- INPUT 0 0 0 1 LDDR2
11 - - A -- INPUT 0 0 0 4 LDRI
13 - - A -- INPUT 0 0 0 8 M
124 - - - -- INPUT 0 0 0 9 MEMENAB
97 - - A -- INPUT 0 0 0 8 MUL
130 - - - 14 INPUT 0 0 0 1 N0
42 - - - 19 INPUT 0 0 0 1 N1
132 - - - 16 INPUT 0 0 0 1 N2
43 - - - 18 INPUT 0 0 0 1 N3
51 - - - 13 INPUT 0 0 0 1 N4
48 - - - 15 INPUT 0 0 0 1 N5
68 - - - 07 INPUT 0 0 0 1 N6
128 - - - 13 INPUT 0 0 0 1 N7
125 - - - -- INPUT 0 0 0 8 PC-BUS
56 - - - -- INPUT 0 0 0 9 RD
117 - - - 06 INPUT 0 0 0 13 RI-BUS
19 - - B -- INPUT 0 0 0 2 SELRI
126 - - - -- INPUT 0 0 0 8 SW-BUS
14 - - A -- INPUT 0 0 0 8 S0
102 - - A -- INPUT 0 0 0 8 S1
8 - - A -- INPUT 0 0 0 8 S2
7 - - A -- INPUT 0 0 0 8 S3
12 - - A -- INPUT 0 0 0 6 T2
70 - - - 05 INPUT 0 0 0 2 T3
112 - - - 03 INPUT 0 0 0 1 WE
54 - - - -- INPUT G 0 0 0 0 161CLRN
141 - - - 22 INPUT 0 0 0 8 161LDN
113 - - - 03 INPUT 0 0 0 1 161PC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\computer\alu\yunsuan22.rpt
yunsuan22
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - C -- OUTPUT 0 1 0 0 ADR0
79 - - C -- OUTPUT 0 1 0 0 ADR1
63 - - - 11 OUTPUT 0 1 0 0 ADR2
80 - - C -- OUTPUT 0 1 0 0 ADR3
78 - - C -- OUTPUT 0 1 0 0 ADR4
82 - - C -- OUTPUT 0 1 0 0 ADR5
29 - - C -- OUTPUT 0 1 0 0 ADR6
83 - - C -- OUTPUT 0 1 0 0 ADR7
46 - - - 17 OUTPUT 0 1 0 0 BUS0
49 - - - 14 OUTPUT 0 1 0 0 BUS1
9 - - A -- OUTPUT 0 1 0 0 BUS2
10 - - A -- OUTPUT 0 1 0 0 BUS3
142 - - - 23 OUTPUT 0 1 0 0 BUS4
140 - - - 21 OUTPUT 0 1 0 0 BUS5
100 - - A -- OUTPUT 0 1 0 0 BUS6
96 - - A -- OUTPUT 0 1 0 0 BUS7
30 - - C -- OUTPUT 0 1 0 0 P1
28 - - C -- OUTPUT 0 1 0 0 P2
31 - - C -- OUTPUT 0 1 0 0 P3
27 - - C -- OUTPUT 0 1 0 0 P4
33 - - C -- OUTPUT 0 1 0 0 P5
32 - - C -- OUTPUT 0 1 0 0 P6
26 - - C -- OUTPUT 0 1 0 0 P7
144 - - - 24 OUTPUT 0 1 0 0 P8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\yunsuan22.rpt
yunsuan22
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 5 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_0
- - 3 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_1
- - 4 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_2
- - 8 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_3
- - 1 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_4
- - 2 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_5
- - 7 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_6
- - 6 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:92|altram:sram|segment0_7
- 1 - C 09 AND2 3 0 0 8 |LPM_RAM_IO:92|:91
- 1 - A 14 OR2 0 4 0 1 |MULTI:161|one_bit_adder:U_0_0|:7
- 3 - A 13 AND2 0 4 0 2 |MULTI:161|one_bit_adder:U_0_0|:12
- 2 - A 13 OR2 s 0 4 0 2 |MULTI:161|one_bit_adder:U_0_1|~8~1
- 7 - A 13 AND2 0 3 0 2 |MULTI:161|one_bit_adder:U_0_1|:12
- 5 - A 13 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_0_2|:8
- 4 - A 13 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_0_2|:13
- 8 - A 13 OR2 0 4 0 1 |MULTI:161|one_bit_adder:U_0_2|:14
- 6 - A 13 OR2 0 4 0 4 |MULTI:161|one_bit_adder:U_0_2|:15
- 2 - A 20 OR2 0 3 0 4 |MULTI:161|one_bit_adder:U_0_3|:13
- 2 - A 23 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_0_4|:8
- 1 - A 23 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_0_4|:13
- 4 - A 23 OR2 0 4 0 1 |MULTI:161|one_bit_adder:U_0_4|:14
- 5 - A 23 OR2 0 4 0 1 |MULTI:161|one_bit_adder:U_0_4|:15
- 4 - A 15 OR2 0 4 0 1 |MULTI:161|one_bit_adder:U_1_0|:7
- 5 - A 15 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_1_0|:12
- 1 - A 15 OR2 0 4 0 3 |MULTI:161|one_bit_adder:U_1_1|:8
- 8 - A 15 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_1_1|:15
- 3 - A 15 OR2 0 4 0 3 |MULTI:161|one_bit_adder:U_1_2|:8
- 6 - A 15 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_1_2|:15
- 8 - A 23 OR2 0 4 0 2 |MULTI:161|one_bit_adder:U_1_3|:8
- 7 - A 23 OR2 0 4 0 1 |MULTI:161|one_bit_adder:U_1_3|:15
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