📄 yunsuan22.rpt
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Project Information d:\computer\alu\yunsuan22.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 10/15/2006 01:36:13
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
yunsuan22
EPF10K10TC144-3 37 24 0 2048 33 % 222 38 %
User Pins: 37 24 0
Project Information d:\computer\alu\yunsuan22.rpt
** PROJECT COMPILATION MESSAGES **
Warning: LATCH '|74373:97|:12' is permanently enabled
Warning: LATCH '|74373:97|:15' is permanently enabled
Warning: LATCH '|74373:97|:16' is permanently enabled
Warning: LATCH '|74373:97|:14' is permanently enabled
Warning: LATCH '|74373:97|:13' is permanently enabled
Warning: LATCH '|74373:97|:19' is permanently enabled
Warning: LATCH '|74373:97|:18' is permanently enabled
Warning: LATCH '|74373:97|:17' is permanently enabled
Project Information d:\computer\alu\yunsuan22.rpt
** EMBEDDED ARRAYS **
|LPM_RAM_IO:92|altram:sram|content: MEMORY (
width = 8;
depth = 256;
segmentsize = 256;
mode = MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0;
)
OF SEGMENTS (
|LPM_RAM_IO:92|altram:sram|segment0_7,
|LPM_RAM_IO:92|altram:sram|segment0_6,
|LPM_RAM_IO:92|altram:sram|segment0_5,
|LPM_RAM_IO:92|altram:sram|segment0_4,
|LPM_RAM_IO:92|altram:sram|segment0_3,
|LPM_RAM_IO:92|altram:sram|segment0_2,
|LPM_RAM_IO:92|altram:sram|segment0_1,
|LPM_RAM_IO:92|altram:sram|segment0_0
);
Project Information d:\computer\alu\yunsuan22.rpt
** FILE HIERARCHY **
|74244:82|
|74244:182|
|74244:183|
|74244:184|
|74273:83|
|74273:176|
|74273:177|
|74161:78|
|74161:78|f74161:sub|
|74161:79|
|74161:79|f74161:sub|
|lpm_ram_io:92|
|lpm_ram_io:92|altram:sram|
|74373:97|
|74374:178|
|74374:179|
|74374:180|
|74374:181|
|74181:174|
|74181:175|
|multi:161|
|multi:161|one_bit_adder:U_0_0|
|multi:161|one_bit_adder:U_0_1|
|multi:161|one_bit_adder:U_0_2|
|multi:161|one_bit_adder:U_0_3|
|multi:161|one_bit_adder:U_0_4|
|multi:161|one_bit_adder:U_0_5|
|multi:161|one_bit_adder:U_1_0|
|multi:161|one_bit_adder:U_1_1|
|multi:161|one_bit_adder:U_1_2|
|multi:161|one_bit_adder:U_1_3|
|multi:161|one_bit_adder:U_1_4|
|multi:161|one_bit_adder:U_1_5|
|multi:161|one_bit_adder:U_2_0|
|multi:161|one_bit_adder:U_2_1|
|multi:161|one_bit_adder:U_2_2|
|multi:161|one_bit_adder:U_2_3|
|multi:161|one_bit_adder:U_2_4|
|multi:161|one_bit_adder:U_2_5|
|multi:161|one_bit_adder:U_3_0|
|multi:161|one_bit_adder:U_3_1|
|multi:161|one_bit_adder:U_3_2|
|multi:161|one_bit_adder:U_3_3|
|multi:161|one_bit_adder:U_3_4|
|multi:161|one_bit_adder:U_3_5|
|multi:161|one_bit_adder:U_4_0|
|multi:161|one_bit_adder:U_4_1|
|multi:161|one_bit_adder:U_4_2|
|multi:161|one_bit_adder:U_4_3|
|multi:161|one_bit_adder:U_4_4|
|multi:161|one_bit_adder:U_4_5|
|74257:159|
|74257:160|
|risel:186|
|risel:186|2sel1:17|
|risel:186|4sel1:12|
Device-Specific Information: d:\computer\alu\yunsuan22.rpt
yunsuan22
***** Logic for device 'yunsuan22' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R
E E E E E E E M E E E E E E E E E
S 1 S S S S S S G S P E V S S S S R S S S S S
E 6 G E E E E V E E G N W C M C E E E E I E V E 1 E E E
R B 1 B N R R R R C R R N D - - E C R R R R L - R C R 6 R R R
V U L U D V V V V C V V D I B B N I V V V V D B V C V 1 V V V
P E S D S I E E E E I E N E N I N N U U A N E E E E A U E I E P W E E E
8 D 4 N 5 O D D D D O D 2 D 0 O 7 T S S B T D D D D R S D O D C E D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
S3 | 7 102 | S1
S2 | 8 101 | RESERVED
BUS2 | 9 100 | BUS6
BUS3 | 10 99 | LDDR2
LDRI | 11 98 | CN
T2 | 12 97 | MUL
M | 13 96 | BUS7
S0 | 14 95 | LDDR1
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
DAT1 | 17 92 | RESERVED
RESERVED | 18 91 | DAT0
SELRI | 19 EPF10K10TC144-3 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
DAT2 | 22 87 | RESERVED
RESERVED | 23 86 | DAT3
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
P7 | 26 83 | ADR7
P4 | 27 82 | ADR5
P2 | 28 81 | ADR0
ADR6 | 29 80 | ADR3
P1 | 30 79 | ADR1
P3 | 31 78 | ADR4
P6 | 32 77 | ^MSEL0
P5 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
ALU-BUS | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R N N R V B R N B G N V V 1 C R G G R R V R A R R G R N R T V R
E E E N E 1 3 E C U E 5 U N 4 C C 6 L D N N E E C E D E E N E 6 E 3 C E
S S S D S S C S S S D C C 1 K D D S S C S R S S D S S C S
E E E I E E I 0 E 1 I I I C - I I E E I E 2 E E I E E I E
R R R O R R O R O N N L C N N R R O R R R O R R O R
V V V V V V T T R D T T V V V V V V V V
E E E E E E N U E E E E E E E E
D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
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