lzcpu.rpt
来自「vhd语言」· RPT 代码 · 共 946 行 · 第 1/5 页
RPT
946 行
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 7 8 8 8 8 2 8 7 8 8 8 0 7 8 8 8 8 8 4 8 8 1 8 8 172/0
B: 8 8 8 8 7 3 8 5 8 0 8 0 0 2 8 3 7 8 8 5 2 0 6 8 8 136/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 7 3 0 14/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 8 1 0 3 3 8 0 8 38/0
E: 0 0 0 8 0 0 8 0 8 8 2 0 8 8 8 5 5 7 8 7 7 2 4 8 2 105/8
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 6 7 8 7 2 7 2 1 2 2 46/0
Total: 16 15 16 24 15 11 18 13 23 16 18 8 8 21 26 29 27 39 32 18 27 15 27 29 28 511/8
Device-Specific Information: c:\maxplus2\multi\cpu\lzcpu.rpt
lzcpu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - - 13 INPUT 0 0 0 16 CLK-CDU
128 - - - 13 INPUT 0 0 0 3 CLKJP
89 - - C -- INPUT 0 0 0 8 CLR-CDU
70 - - - 05 INPUT 0 0 0 43 CLRKONG
92 - - C -- INPUT 0 0 0 1 DP
88 - - D -- INPUT 0 0 0 6 EN-CDU
95 - - B -- INPUT 0 0 0 1 QD
125 - - - -- INPUT G 0 0 0 0 SHUCLK
90 - - C -- INPUT 0 0 0 1 TJ
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\multi\cpu\lzcpu.rpt
lzcpu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
31 - - F -- OUTPUT 0 1 0 0 ADR0
32 - - F -- OUTPUT 0 1 0 0 ADR1
33 - - F -- OUTPUT 0 1 0 0 ADR2
36 - - - 24 OUTPUT 0 1 0 0 ADR3
37 - - - 23 OUTPUT 0 1 0 0 ADR4
38 - - - 22 OUTPUT 0 1 0 0 ADR5
39 - - - 21 OUTPUT 0 1 0 0 ADR6
41 - - - 20 OUTPUT 0 1 0 0 ADR7
83 - - E -- OUTPUT 0 1 0 0 AD0
82 - - E -- OUTPUT 0 1 0 0 AD1
81 - - F -- OUTPUT 0 1 0 0 AD2
80 - - F -- OUTPUT 0 1 0 0 AD3
79 - - F -- OUTPUT 0 1 0 0 AD4
78 - - F -- OUTPUT 0 1 0 0 AD5
21 - - D -- OUTPUT 0 1 0 0 BUS0
22 - - D -- OUTPUT 0 1 0 0 BUS1
23 - - D -- OUTPUT 0 1 0 0 BUS2
26 - - E -- OUTPUT 0 1 0 0 BUS3
27 - - E -- OUTPUT 0 1 0 0 BUS4
28 - - E -- OUTPUT 0 1 0 0 BUS5
29 - - E -- OUTPUT 0 1 0 0 BUS6
30 - - F -- OUTPUT 0 1 0 0 BUS7
8 - - A -- OUTPUT 0 1 0 0 L0
102 - - A -- OUTPUT 0 1 0 0 L1
100 - - A -- OUTPUT 0 1 0 0 L2
99 - - B -- OUTPUT 0 1 0 0 L3
97 - - B -- OUTPUT 0 1 0 0 L4
96 - - B -- OUTPUT 0 1 0 0 L5
43 - - - 18 OUTPUT 0 1 0 0 OUT0
44 - - - 18 OUTPUT 0 1 0 0 OUT1
46 - - - 17 OUTPUT 0 1 0 0 OUT2
47 - - - 16 OUTPUT 0 1 0 0 OUT3
48 - - - 15 OUTPUT 0 1 0 0 OUT4
49 - - - 14 OUTPUT 0 1 0 0 OUT5
51 - - - 14 OUTPUT 0 1 0 0 OUT6
18 - - D -- OUTPUT 0 1 0 0 P1
19 - - D -- OUTPUT 0 1 0 0 P2
20 - - D -- OUTPUT 0 1 0 0 P3
9 - - B -- OUTPUT 0 1 0 0 T1
10 - - B -- OUTPUT 0 1 0 0 T2
12 - - C -- OUTPUT 0 1 0 0 T3
13 - - C -- OUTPUT 0 1 0 0 T4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\multi\cpu\lzcpu.rpt
lzcpu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 16 OR2 0 3 0 1 |kongceshi2:8|p1:8|:4
- 2 - D 20 OR2 0 3 0 1 |kongceshi2:8|p1:8|:5
- 6 - A 23 OR2 0 3 0 1 |kongceshi2:8|p1:8|:6
- 4 - F 16 OR2 0 3 0 1 |kongceshi2:8|p1:8|:12
- 6 - A 02 DFFE 1 5 1 29 |kongceshi2:8|p1:8|7474:1|1Q (|kongceshi2:8|p1:8|7474:1|:9)
- 4 - A 01 DFFE 1 5 1 22 |kongceshi2:8|p1:8|7474:1|2Q (|kongceshi2:8|p1:8|7474:1|:10)
- 2 - F 22 DFFE 1 5 0 1 |kongceshi2:8|p1:8|7474:2|1Q (|kongceshi2:8|p1:8|7474:2|:9)
- 6 - D 20 DFFE 1 5 0 1 |kongceshi2:8|p1:8|7474:2|2Q (|kongceshi2:8|p1:8|7474:2|:10)
- 7 - A 23 DFFE 1 5 0 1 |kongceshi2:8|p1:8|7474:3|1Q (|kongceshi2:8|p1:8|7474:3|:9)
- 5 - F 16 DFFE 1 4 0 1 |kongceshi2:8|p1:8|7474:3|2Q (|kongceshi2:8|p1:8|7474:3|:10)
- 8 - D 22 OR2 0 3 0 1 |kongceshi2:8|p2:7|:10
- 6 - D 17 OR2 0 3 0 1 |kongceshi2:8|p2:7|:11
- 4 - D 22 DFFE 1 5 0 1 |kongceshi2:8|p2:7|7474:8|1Q (|kongceshi2:8|p2:7|7474:8|:9)
- 7 - D 17 DFFE 1 5 0 1 |kongceshi2:8|p2:7|7474:8|2Q (|kongceshi2:8|p2:7|7474:8|:10)
- 7 - A 16 OR2 0 3 0 1 |kongceshi2:8|p3:6|:10
- 2 - D 17 OR2 0 3 0 1 |kongceshi2:8|p3:6|:11
- 8 - A 16 DFFE 1 5 0 1 |kongceshi2:8|p3:6|7474:8|1Q (|kongceshi2:8|p3:6|7474:8|:9)
- 1 - D 18 DFFE 1 5 0 1 |kongceshi2:8|p3:6|7474:8|2Q (|kongceshi2:8|p3:6|7474:8|:10)
- 4 - A 23 DFFE 1 4 0 1 |kongceshi2:8|p3:6|7474:9|1Q (|kongceshi2:8|p3:6|7474:9|:9)
- 7 - F 16 DFFE 1 3 0 1 |kongceshi2:8|p3:6|7474:9|2Q (|kongceshi2:8|p3:6|7474:9|:10)
- 6 - A 19 OR2 ! 0 3 0 13 |kongceshi2:8|ROM:2|:146
- 8 - A 19 AND2 0 4 0 10 |kongceshi2:8|ROM:2|:153
- 6 - A 14 AND2 0 4 0 9 |kongceshi2:8|ROM:2|:160
- 1 - A 19 AND2 0 4 0 3 |kongceshi2:8|ROM:2|:174
- 5 - A 03 AND2 s ! 0 3 0 8 |kongceshi2:8|ROM:2|~181~1
- 5 - A 14 AND2 0 4 0 2 |kongceshi2:8|ROM:2|:181
- 4 - A 14 OR2 s 0 2 0 9 |kongceshi2:8|ROM:2|~188~1
- 7 - A 14 AND2 0 3 0 1 |kongceshi2:8|ROM:2|:188
- 5 - A 21 AND2 0 4 0 4 |kongceshi2:8|ROM:2|:195
- 8 - A 20 OR2 s 0 2 0 7 |kongceshi2:8|ROM:2|~202~1
- 5 - A 13 AND2 0 4 0 4 |kongceshi2:8|ROM:2|:202
- 3 - A 13 AND2 s ! 0 2 0 5 |kongceshi2:8|ROM:2|~209~1
- 2 - A 13 AND2 0 3 0 4 |kongceshi2:8|ROM:2|:209
- 3 - A 14 AND2 0 4 0 3 |kongceshi2:8|ROM:2|:216
- 4 - A 21 OR2 s 0 2 0 10 |kongceshi2:8|ROM:2|~223~1
- 5 - A 20 AND2 0 4 0 3 |kongceshi2:8|ROM:2|:223
- 7 - A 20 AND2 0 4 0 5 |kongceshi2:8|ROM:2|:230
- 2 - A 03 AND2 0 4 0 6 |kongceshi2:8|ROM:2|:237
- 6 - A 12 AND2 0 3 0 6 |kongceshi2:8|ROM:2|:244
- 3 - A 03 AND2 0 4 0 6 |kongceshi2:8|ROM:2|:251
- 2 - A 21 AND2 s ! 0 3 0 1 |kongceshi2:8|ROM:2|~258~1
- 1 - A 21 AND2 0 3 0 6 |kongceshi2:8|ROM:2|:258
- 5 - A 10 AND2 0 4 0 12 |kongceshi2:8|ROM:2|:265
- 2 - A 10 AND2 s 0 3 0 4 |kongceshi2:8|ROM:2|~272~1
- 4 - A 13 AND2 s 0 2 0 1 |kongceshi2:8|ROM:2|~272~2
- 3 - A 10 AND2 0 4 0 11 |kongceshi2:8|ROM:2|:272
- 1 - A 10 AND2 0 4 0 10 |kongceshi2:8|ROM:2|:279
- 4 - A 20 AND2 0 4 0 8 |kongceshi2:8|ROM:2|:286
- 5 - A 12 AND2 0 4 0 10 |kongceshi2:8|ROM:2|:293
- 7 - A 12 AND2 s 0 4 0 2 |kongceshi2:8|ROM:2|~300~1
- 3 - A 21 OR2 s ! 0 2 0 1 |kongceshi2:8|ROM:2|~300~2
- 1 - A 12 AND2 0 3 0 9 |kongceshi2:8|ROM:2|:300
- 3 - A 12 AND2 0 4 0 9 |kongceshi2:8|ROM:2|:307
- 6 - A 21 AND2 0 4 0 8 |kongceshi2:8|ROM:2|:314
- 6 - A 10 AND2 0 4 0 7 |kongceshi2:8|ROM:2|:321
- 7 - A 21 OR2 s ! 0 2 0 6 |kongceshi2:8|ROM:2|~328~1
- 6 - A 20 AND2 0 4 0 8 |kongceshi2:8|ROM:2|:328
- 1 - A 20 OR2 ! 0 4 0 7 |kongceshi2:8|ROM:2|:335
- 7 - A 13 AND2 0 4 0 7 |kongceshi2:8|ROM:2|:342
- 2 - A 12 OR2 s ! 0 2 0 6 |kongceshi2:8|ROM:2|~349~1
- 4 - A 12 OR2 ! 0 4 0 6 |kongceshi2:8|ROM:2|:349
- 2 - A 20 AND2 0 4 0 7 |kongceshi2:8|ROM:2|:356
- 8 - A 21 OR2 ! 0 4 0 4 |kongceshi2:8|ROM:2|:363
- 6 - A 13 AND2 0 4 0 5 |kongceshi2:8|ROM:2|:370
- 8 - A 12 OR2 ! 0 4 0 3 |kongceshi2:8|ROM:2|:377
- 1 - A 13 AND2 0 4 0 5 |kongceshi2:8|ROM:2|:384
- 6 - A 03 AND2 0 4 0 4 |kongceshi2:8|ROM:2|:391
- 7 - A 03 AND2 s 0 2 0 4 |kongceshi2:8|ROM:2|~398~1
- 1 - A 03 AND2 0 4 0 6 |kongceshi2:8|ROM:2|:398
- 2 - A 07 OR2 s 0 3 0 2 |kongceshi2:8|ROM:2|~624~1
- 6 - A 11 AND2 s ! 0 2 0 2 |kongceshi2:8|ROM:2|~624~2
- 8 - A 03 OR2 0 3 0 3 |kongceshi2:8|ROM:2|:633
- 4 - A 08 OR2 0 3 0 1 |kongceshi2:8|ROM:2|:639
- 5 - A 08 OR2 0 3 0 1 |kongceshi2:8|ROM:2|:645
- 2 - A 08 OR2 0 4 0 1 |kongceshi2:8|ROM:2|:659
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