lzcpu.rpt
来自「vhd语言」· RPT 代码 · 共 946 行 · 第 1/5 页
RPT
946 行
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | L1
L0 | 8 101 | RESERVED
T1 | 9 100 | L2
T2 | 10 99 | L3
RESERVED | 11 98 | RESERVED
T3 | 12 97 | L4
T4 | 13 96 | L5
RESERVED | 14 95 | QD
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | DP
P1 | 18 91 | RESERVED
P2 | 19 EPF10K20TI144-4 90 | TJ
P3 | 20 89 | CLR-CDU
BUS0 | 21 88 | EN-CDU
BUS1 | 22 87 | RESERVED
BUS2 | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
BUS3 | 26 83 | AD0
BUS4 | 27 82 | AD1
BUS5 | 28 81 | AD2
BUS6 | 29 80 | AD3
BUS7 | 30 79 | AD4
ADR0 | 31 78 | AD5
ADR1 | 32 77 | ^MSEL0
ADR2 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
ADR3 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
A A A G A R O O V O O O O G O V V G G G G G R R V R R R R G R R R C V R
D D D N D E U U C U U U U N U C C N N N N N E E C E E E E N E E E L C E
R R R D R S T T C T T T T D T C C D D D D D S S C S S S S D S S S R C S
4 5 6 I 7 E 0 1 I 2 3 4 5 I 6 I I I I I I I E E I E E E E I E E E K I E
O R O O N N N N N N N R R O R R R R O R R R O O R
V T T T T T T T V V V V V V V V V N V
E E E E E E E E E E G E
D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\maxplus2\multi\cpu\lzcpu.rpt
lzcpu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 14/22( 63%)
A2 7/ 8( 87%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 13/22( 59%)
A3 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
A4 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
A5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
A6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
A7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A9 7/ 8( 87%) 3/ 8( 37%) 1/ 8( 12%) 1/2 1/2 13/22( 59%)
A10 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
A11 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 1/2 1/2 15/22( 68%)
A12 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
A13 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
A14 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 1/2 1/2 6/22( 27%)
A15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
A16 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 2/2 19/22( 86%)
A17 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 16/22( 72%)
A18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A19 4/ 8( 50%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 5/22( 22%)
A20 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 1/2 1/2 6/22( 27%)
A21 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/22( 36%)
A22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 2/2 17/22( 77%)
A24 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 18/22( 81%)
B1 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B2 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
B3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
B4 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
B5 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 14/22( 63%)
B6 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
B7 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 6/22( 27%)
B8 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B9 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
B11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
B13 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B14 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
B15 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B16 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
B17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
B18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
B19 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B20 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B22 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B23 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 14/22( 63%)
B24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C13 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
C22 7/ 8( 87%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
C23 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
D15 7/ 8( 87%) 7/ 8( 87%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
D17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 2/2 14/22( 63%)
D18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 2/2 6/22( 27%)
D20 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 2/2 2/2 9/22( 40%)
D21 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
D22 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 2/2 12/22( 54%)
D24 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
E4 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 9/22( 40%)
E7 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
E9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
E10 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 11/22( 50%)
E11 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
E13 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
E14 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 10/22( 45%)
E15 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 10/22( 45%)
E16 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 9/22( 40%)
E17 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%)
E18 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
E19 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%)
E20 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
E21 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
E22 4/ 8( 50%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 8/22( 36%)
E23 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 10/22( 45%)
E24 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
F14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F15 6/ 8( 75%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F16 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 2/2 11/22( 50%)
F17 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
F18 7/ 8( 87%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F19 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F20 7/ 8( 87%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
F21 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F22 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 2/2 6/22( 27%)
F23 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F24 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
E25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 1/2 2/2 18/22( 81%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 50/96 ( 52%)
Total logic cells used: 511/1152 ( 44%)
Total embedded cells used: 8/48 ( 16%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 3.04/4 ( 76%)
Total fan-in: 1554/4608 ( 33%)
Total input pins required: 9
Total input I/O cell registers required: 0
Total output pins required: 42
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 511
Total flipflops required: 126
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 108/1152 ( 9%)
Logic Cell and Embedded Cell Counts
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