lzcpu.rpt

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Project Information                            c:\maxplus2\multi\cpu\lzcpu.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/18/2006 18:06:01

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

lzcpu     EPF10K20TI144-4  9      42     0    2048      16 %    511      44 %

User Pins:                 9      42     0  



Project Information                            c:\maxplus2\multi\cpu\lzcpu.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop '|kongceshi2:8|74273:63|:18' stuck at GND
Warning: LATCH '|yunsuan11:10|74373:97|:19' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:16' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:17' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:18' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:15' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:13' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:14' is permanently enabled
Warning: LATCH '|yunsuan11:10|74373:97|:12' is permanently enabled


Project Information                            c:\maxplus2\multi\cpu\lzcpu.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

lzcpu@31                          ADR0
lzcpu@32                          ADR1
lzcpu@33                          ADR2
lzcpu@36                          ADR3
lzcpu@37                          ADR4
lzcpu@38                          ADR5
lzcpu@39                          ADR6
lzcpu@41                          ADR7
lzcpu@83                          AD0
lzcpu@82                          AD1
lzcpu@81                          AD2
lzcpu@80                          AD3
lzcpu@79                          AD4
lzcpu@78                          AD5
lzcpu@21                          BUS0
lzcpu@22                          BUS1
lzcpu@23                          BUS2
lzcpu@26                          BUS3
lzcpu@27                          BUS4
lzcpu@28                          BUS5
lzcpu@29                          BUS6
lzcpu@30                          BUS7
lzcpu@122                         CLK-CDU
lzcpu@128                         CLKJP
lzcpu@89                          CLR-CDU
lzcpu@70                          CLRKONG
lzcpu@92                          DP
lzcpu@88                          EN-CDU
lzcpu@8                           L0
lzcpu@102                         L1
lzcpu@100                         L2
lzcpu@99                          L3
lzcpu@97                          L4
lzcpu@96                          L5
lzcpu@43                          OUT0
lzcpu@44                          OUT1
lzcpu@46                          OUT2
lzcpu@47                          OUT3
lzcpu@48                          OUT4
lzcpu@49                          OUT5
lzcpu@51                          OUT6
lzcpu@18                          P1
lzcpu@19                          P2
lzcpu@20                          P3
lzcpu@95                          QD
lzcpu@125                         SHUCLK
lzcpu@90                          TJ
lzcpu@9                           T1
lzcpu@10                          T2
lzcpu@12                          T3
lzcpu@13                          T4


Project Information                            c:\maxplus2\multi\cpu\lzcpu.rpt

** STATE MACHINE ASSIGNMENTS **


|xianshi:9|mulx:41|mulx6:2|SS: MACHINE
        OF BITS (
           |xianshi:9|mulx:41|mulx6:2|SS~6,
           |xianshi:9|mulx:41|mulx6:2|SS~5,
           |xianshi:9|mulx:41|mulx6:2|SS~4,
           |xianshi:9|mulx:41|mulx6:2|SS~3,
           |xianshi:9|mulx:41|mulx6:2|SS~2,
           |xianshi:9|mulx:41|mulx6:2|SS~1
        )
        WITH STATES (
                              S0 = B"000000", 
                              S1 = B"110000", 
                              S2 = B"101000", 
                              S3 = B"100100", 
                              S4 = B"100010", 
                              S5 = B"100001"
);



Project Information                            c:\maxplus2\multi\cpu\lzcpu.rpt

** EMBEDDED ARRAYS **


|yunsuan11:10|LPM_RAM_IO:92|altram:sram|content: MEMORY (
               width        =    8;
               depth        =  256;
               segmentsize  =  256;
               mode         = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0;
               file         = "c:\maxplus2\multi\cpu\lxzhprogram.mif";
         )
         OF SEGMENTS (
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_7,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_6,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_5,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_4,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_3,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_2,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_1,
               |yunsuan11:10|LPM_RAM_IO:92|altram:sram|segment0_0
);




Project Information                            c:\maxplus2\multi\cpu\lzcpu.rpt

** FILE HIERARCHY **



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