graycounter_2.v

来自「异步fifo的verilog程序」· Verilog 代码 · 共 39 行

//FILE NAME: GrayCounter_2
//AUTHOR:    jialiang

`timescale 1ns/1ns
module GrayCounter_2(
    gray_out,
    bin_addr,
    enable,
    rst,
    clk
    );
    
  parameter   COUNTER_WIDTH = 7 ;
   
  output   [COUNTER_WIDTH-1:0]    gray_out;  //'Gray' code count output.
  output   [COUNTER_WIDTH-2:0]    bin_addr;
    
  input                           enable;    //Count enable.
  input                           rst;       //Count reset.
  input                           clk; 

  reg      [COUNTER_WIDTH-1:0]    gray_out;
  reg      [COUNTER_WIDTH-1:0]    bin;

  assign  bin_addr = bin[COUNTER_WIDTH-2:0];
 
  always @ (posedge clk or negedge rst) begin
     if (!rst) begin
         bin      <= 1;   
         gray_out <= 0;      
     end
     else if (enable) begin
         bin   <= bin + 1;
         gray_out <= (bin>>1)^bin;
     end
   end  //end always @(posedge clk or negedge rst)
    
endmodule