uart.tan.summary

vhdl书写uart代码,经验证功能非常的全.

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.327 ns
From           : send
To             : uart_core:U_Core|si_count[3]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.946 ns
From           : shift_register:U_SR|dout
To             : TxD
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 5.829 ns
From           : reset_n
To             : shift_register:U_SR|shift_regs[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 80.61 MHz ( period = 12.405 ns )
From           : counter:U_Counter|overflow
To             : uart_core:U_Core|si_count[3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : uart_core:U_Core|ce_parts
To             : counter:U_Counter|count[11]
From Clock     : clk
To Clock       : clk
Failed Paths   : 47

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 47

--------------------------------------------------------------------------------------