switch.vhd

VHDL实现循环码编码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity switch is
	port
	(	ch		:in  std_logic;
		i1		:in  std_logic;
		i2		:in  std_logic;
		o1		:out std_logic;
		o2		:out std_logic);
end switch;

architecture behave_switch of switch is
begin
	process
	begin
	if (ch='0') then
		o1<=i1 XOR i2;
		o2<='0';
	elsif (ch='1') then
		o1<='0';
		o2<=i1 XOR i2;
	end if;
	end process;
end behave_switch;