addvb_models_9.doc

VerilogHDL_advanced_digital_design_code_Ch9 VerilogHDL高级数字设计源码Ch9

vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|09 Aug 2003 18:16:46 -0000
vti_extenderversion:SR|5.0.2.4330
vti_author:SR|EAS\\ciletti
vti_modifiedby:SR|EAS\\ciletti
vti_timecreated:TR|09 Aug 2003 18:16:46 -0000
vti_cacheddtm:TX|09 Aug 2003 18:16:46 -0000
vti_filesize:IR|273408
vti_cachedtitle:SR|- sined number representation
vti_title:SR|- sined number representation
vti_lineageid:SR|{15A44B9E-EA3E-4785-88D7-405133785FC4}
vti_backlinkinfo:VX|