image_converter_2.v

VerilogHDL_advanced_digital_design_code_Ch9 VerilogHDL高级数字设计源码Ch9

			PP_1_PV = 8'bx; 
			end

endcase
end

always @ (index_2) begin
case (index_2)
9, 10, 11, 12, 13, 14: 	begin 	
			PP_2_Err_1 = Err_Row_2[index_2-1-8]; 	PP_2_Err_2 = Err_Row_1[index_2-1-8];
			PP_2_Err_3 = Err_Row_1[index_2-8]; 	PP_2_Err_4 = Err_Row_1[index_2+1-8];
			PP_2_PV = PV_Row_2[index_2-8]; 
			end

21, 22:			begin 	
			PP_2_Err_1 = Err_Row_3[index_2-1-16]; 	PP_2_Err_2 = Err_Row_2[index_2-1-16];
			PP_2_Err_3 = Err_Row_2[index_2-16]; 	PP_2_Err_4 = Err_Row_2[index_2+1-16];
			PP_2_PV = PV_Row_3[index_2-16]; 
			end

29, 30, 31, 32: 		begin 	
			PP_2_Err_1 = Err_Row_4[index_2-1-24]; 	PP_2_Err_2 = Err_Row_3[index_2-1-24];
			PP_2_Err_3 = Err_Row_3[index_2-24]; 	PP_2_Err_4 = Err_Row_3[index_2+1-24];
			PP_2_PV = PV_Row_4[index_2-24]; 
			end

default: 			begin 	
			PP_2_Err_1 = 8'bx; 	PP_2_Err_2 = 8'bx;
			PP_2_Err_3 = 8'bx; 	PP_2_Err_4 = 8'bx;
			PP_2_PV = 8'bx; 
			end
endcase
end

always @ (index_3) begin
case (index_3)
17, 18, 19, 20:	  	begin 	
			PP_3_Err_1 = Err_Row_3[index_3-1-16]; 	PP_3_Err_2 = Err_Row_2[index_3-1-16];
			PP_3_Err_3 = Err_Row_2[index_3-16]; 	PP_3_Err_4 = Err_Row_2[index_3+1-16];
			PP_3_PV = PV_Row_3[index_3-16]; 
			end

 27,  28:			begin	
			PP_3_Err_1 = Err_Row_4[index_3-1-24]; 	PP_3_Err_2 = Err_Row_3[index_3-1-24];
			PP_3_Err_3 = Err_Row_3[index_3-24]; 	PP_3_Err_4 = Err_Row_3[index_3+1-24];
			PP_3_PV = PV_Row_4[index_3-24]; 
			end

35, 36, 37, 38, 39, 40:	begin 	
			PP_3_Err_1 = Err_Row_5[index_3-1-32]; 	PP_3_Err_2 = Err_Row_4[index_3-1-32];
			PP_3_Err_3 = Err_Row_4[index_3-32]; 	PP_3_Err_4 = Err_Row_4[index_3+1-32];
			PP_3_PV = PV_Row_5[index_3-32]; 
			end

default: 			begin 	
			PP_3_Err_1 = 8'bx; 	PP_3_Err_2 = 8'bx;
			PP_3_Err_3 = 8'bx; 	PP_3_Err_4 = 8'bx;
			PP_3_PV = 8'bx; 
			end
endcase
end

always @ (index_4) begin
case (index_4)
25, 26:	 		begin 	
			PP_4_Err_1 = Err_Row_4[index_4-1-24]; 	PP_4_Err_2 = Err_Row_3[index_4-1-24];
			PP_4_Err_3 = Err_Row_3[index_4-24]; 	PP_4_Err_4 = Err_Row_3[index_4+1-24];
			PP_4_PV = PV_Row_4[index_4-24]; 
			end

33, 34:	 		begin 	
			PP_4_Err_1 = Err_Row_5[index_4-1-32]; 	PP_4_Err_2 = Err_Row_4[index_4-1-32];
			PP_4_Err_3 = Err_Row_4[index_4-32]; 	PP_4_Err_4 = Err_Row_4[index_4+1-32];
			PP_4_PV = PV_Row_5[index_4-32]; 
			end

41, 42, 43, 44, 
45, 46,47, 48: 		begin 	
			PP_4_Err_1 = Err_Row_6[index_4-1-40]; 	PP_4_Err_2 = Err_Row_5[index_4-1-40];
			PP_4_Err_3 = Err_Row_5[index_4-40]; 	PP_4_Err_4 = Err_Row_5[index_4+1-40];
			PP_4_PV = PV_Row_6[index_4-40]; 
			end

default: 			begin 	
			PP_4_Err_1 = 8'bx; 	PP_4_Err_2 = 8'bx;
			PP_4_Err_3 = 8'bx; 	PP_4_Err_4 = 8'bx;
			PP_4_PV = 8'bx; 
			end
endcase
end

always @ (posedge clk ) 
if (Ld_image) begin: Array_Initialization

// Initialize error at left boarder 

  Err_Row_1[0] <= 0;     Err_Row_2[0] <= 0;     Err_Row_3[0] <= 0;
  Err_Row_4[0] <= 0;     Err_Row_5[0] <= 0;     Err_Row_6[0] <= 0;

// Initialize columns in the main array

  Err_Row_1[1] <= 0;  Err_Row_2[1] <= 0;  Err_Row_3[1] <= 0;
  Err_Row_4[1] <= 0;  Err_Row_5[1] <= 0;  Err_Row_6[1] <= 0;

  Err_Row_1[2] <= 0;  Err_Row_2[2] <= 0;  Err_Row_3[2] <= 0;
  Err_Row_4[2] <= 0;  Err_Row_5[2] <= 0;  Err_Row_6[2] <= 0;

  Err_Row_1[3] <= 0;  Err_Row_2[3] <= 0;  Err_Row_3[3] <= 0;
  Err_Row_4[3] <= 0;  Err_Row_5[3] <= 0;  Err_Row_6[3] <= 0;

  Err_Row_1[4] <= 0;  Err_Row_2[4] <= 0;  Err_Row_3[4] <= 0;
  Err_Row_4[4] <= 0;  Err_Row_5[4] <= 0;  Err_Row_6[4] <= 0;

  Err_Row_1[5] <= 0;  Err_Row_2[5] <= 0;  Err_Row_3[5] <= 0;
  Err_Row_4[5] <= 0;  Err_Row_5[5] <= 0;  Err_Row_6[5] <= 0;

  Err_Row_1[6] <= 0;  Err_Row_2[6] <= 0;  Err_Row_3[6] <= 0;
  Err_Row_4[6] <= 0;  Err_Row_5[6] <= 0;  Err_Row_6[6] <= 0;

  Err_Row_1[7] <= 0;  Err_Row_2[7] <= 0;  Err_Row_3[7] <= 0;
  Err_Row_4[7] <= 0;  Err_Row_5[7] <= 0;  Err_Row_6[7] <= 0;

  Err_Row_1[8] <= 0;  Err_Row_2[8] <= 0;  Err_Row_3[8] <= 0;
  Err_Row_4[8] <= 0;  Err_Row_5[8] <= 0;  Err_Row_6[8] <= 0;

// Initalize right boarder

 Err_Row_1[9] <= 0; Err_Row_2[9] <= 0; Err_Row_3[9] <= 0;
 Err_Row_4[9] <= 0; Err_Row_5[9] <= 0; Err_Row_6[9] <= 0;

// Initialize top boarder

 Err_Row_0[0]  <= 0; Err_Row_0[1]  <= 0; Err_Row_0[2]  <= 0; Err_Row_0[3]  <= 0;
 Err_Row_0[4]  <= 0; Err_Row_0[5]  <= 0; Err_Row_0[6]  <= 0; Err_Row_0[7]  <= 0;
 Err_Row_0[8]  <= 0; Err_Row_0[9] <= 0;

// Initalize pixels in the main array

PV_Row_1[1] <= pixel_1; PV_Row_1[2] <= pixel_2; PV_Row_1[3] <= pixel_3; PV_Row_1[4] <= pixel_4;
PV_Row_1[5] <= pixel_5; PV_Row_1[6] <= pixel_6; PV_Row_1[7] <= pixel_7; PV_Row_1[8] <= pixel_8;

PV_Row_2[1] <= pixel_9; PV_Row_2[2] <= pixel_10; PV_Row_2[3] <= pixel_11; PV_Row_2[4] <= pixel_12;
PV_Row_2[5] <= pixel_13; PV_Row_2[6] <= pixel_14; PV_Row_2[7] <= pixel_15; PV_Row_2[8] <= pixel_16;

PV_Row_3[1] <= pixel_17; PV_Row_3[2] <= pixel_18; PV_Row_3[3] <= pixel_19; PV_Row_3[4] <= pixel_20;
PV_Row_3[5] <= pixel_21; PV_Row_3[6] <= pixel_22; PV_Row_3[7] <= pixel_23; PV_Row_3[8] <= pixel_24;

PV_Row_4[1] <= pixel_25; PV_Row_4[2] <= pixel_26; PV_Row_4[3] <= pixel_27; PV_Row_4[4] <= pixel_28;
PV_Row_4[5] <= pixel_29; PV_Row_4[6] <= pixel_30; PV_Row_4[7] <= pixel_31; PV_Row_4[8] <= pixel_32;

PV_Row_5[1] <= pixel_33; PV_Row_5[2] <= pixel_34; PV_Row_5[3] <= pixel_35; PV_Row_5[4] <= pixel_36;
PV_Row_5[5] <= pixel_37; PV_Row_5[6] <= pixel_38; PV_Row_5[7] <= pixel_39; PV_Row_5[8] <= pixel_40;

PV_Row_6[1] <= pixel_41; PV_Row_6[2] <= pixel_42; PV_Row_6[3] <= pixel_43; PV_Row_6[4] <= pixel_44;
PV_Row_6[5] <= pixel_45; PV_Row_6[6] <= pixel_46; PV_Row_6[7] <= pixel_47; PV_Row_6[8] <= pixel_48;
end	// Array_Initialization

else if (Ld_values) begin: Image_Conversion		 
case (index_1)
1, 2, 3, 4, 5, 6, 7, 8: 	begin 	
			Err_Row_1[index_1] <= PP_1_Err_0; HTPV_Row_1[index_1] <= PP_1_HTPV;					end

15, 16:			begin 	
			Err_Row_2[index_1-8] <= PP_1_Err_0; HTPV_Row_2[index_1-8] <= PP_1_HTPV;	
			end

 23, 24: 			begin 
			Err_Row_3[index_1-16] <= PP_1_Err_0; HTPV_Row_3[index_1-16] <= PP_1_HTPV;	
			end
endcase

case (index_2)
9, 10, 11, 12, 13, 14: 	begin 	
			Err_Row_2[index_2 -8] <= PP_2_Err_0; HTPV_Row_2[index_2 -8] <= PP_2_HTPV;				end

21, 22:			begin 	
			Err_Row_3[index_2 -16] <= PP_2_Err_0; HTPV_Row_3[index_2 -16] <= PP_2_HTPV;	
			end

 29, 30, 31, 32:		begin 
			Err_Row_4[index_2 -24] <= PP_2_Err_0; HTPV_Row_4[index_2 -24] <= PP_2_HTPV;	
			end
endcase

case (index_3)
17, 18, 19, 20: 		begin 	
			Err_Row_3[index_3 -16] <= PP_3_Err_0; HTPV_Row_3[index_3 -16] <= PP_3_HTPV;				end

27, 28:			begin 	
			Err_Row_4[index_3 -24] <= PP_3_Err_0; HTPV_Row_4[index_3 -24] <= PP_3_HTPV;	
			end

 35, 36, 37, 38, 39, 40:	begin 
			Err_Row_5[index_3 -32] <= PP_3_Err_0; HTPV_Row_5[index_3 -32] <= PP_3_HTPV;	
			end
endcase

case (index_4)
25, 26: 			begin 	
			Err_Row_4[index_4 - 24] <= PP_4_Err_0; HTPV_Row_4[index_4 -24] <= PP_4_HTPV;				end

33, 34:			begin 	
			Err_Row_5[index_4 -32] <= PP_4_Err_0; HTPV_Row_5[index_4 -32] <= PP_4_HTPV;	
			end

 41, 42, 43, 44, 45, 46, 47, 48:
begin 
			Err_Row_6[index_4 -40] <= PP_4_Err_0; HTPV_Row_6[index_4 -40] <= PP_4_HTPV;	
			end
endcase
end		// Image_Conversion
endmodule