synchro_2.v

来自「Verilog HDL 高级数字设计源码 _chapter5」· Verilog 代码 · 共 15 行

module Synchro_2 (synchro_out, synchro_in, clk, reset);
  output	synchro_out;
  input		synchro_in;
  input		clk, reset;
  reg 		A_temp, synchro_out;
  
  always @ (posedge clk or posedge reset) begin   // Two stage pipeline synchronizer
    if (reset) begin A_temp <= 0; synchro_out <= 0; end
    else begin A_temp <= synchro_in; 
      synchro_out <= A_temp;
    end
 end
endmodule