latch_rbar_ca.v

Verilog HDL 高级数字设计源码 _chapter5

module Latch_Rbar_CA (q_out, data_in, enable, reset);
  output 		q_out;
  input 		data_in, enable, reset;

  assign q_out = !reset ? 0 : enable ? data_in : q_out;
endmodule