compare_2_ca1.txt

来自「Verilog HDL 高级数字设计源码 _chapter5」· 文本 代码 · 共 10 行

module compare_2_CA1  (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0);
  input 		A1, A0, B1, B0;
  output 		A_lt_B, A_gt_B, A_eq_B;

  assign 	A_lt_B = ({A1,A0} < {B1,B0});
  assign 	A_gt_B = ({A1,A0} > {B1,B0});
  assign 	A_eq_B = ({A1,A0} == {B1,B0});
endmodule