compare_2_ca0.v

Verilog HDL 高级数字设计源码 _chapter5

module compare_2_CA0 (A_lt_B, A_gt_B, A_eq_B, A1, A0, B1, B0);
  input 	A1, A0, B1, B0;
  output 	A_lt_B, A_gt_B, A_eq_B;

  assign A_lt_B = (~A1) & B1 | (~A1) & (~A0) & B0 | (~A0) & B1 & B0;

  assign A_gt_B = A1 & (~B1) | A0 & (~B1) & (~B0) | A1 & A0 & (~B0);

  assign A_eq_B = (~A1) & (~A0) & (~B1) & (~B0) | (~A1) & A0 & (~B1) & B0 
| A1 & A0 & B1 & B0 | A1 & (~A0) & B1 & (~B0);

endmodule