📄 alarm_clock.txt
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.P_ALARM.ALL;
ENTITY ALARM_CLOCK IS
PORT(KEYPAD :IN STD_LOGIC_VECTOR(9 DOWNTO 0);
KEY_DOWN :IN STD_LOGIC;
ALARM_BUTTON:IN STD_LOGIC;
TIME_BUTTON :IN STD_LOGIC;
CLK :IN STD_LOGIC;
RESET :IN STD_LOGIC;
DISPLAY :OUT T_DISPLAY;
SOUND_ALARM :OUT STD_LOGIC);
END ENTITY ALARM_CLOCK;
ARCHITECTURE ART OF ALARM_CLOCK IS
COMPONENT DECODER IS
PORT(KEYPAD :IN STD_LOGIC_VECTOR(9 DOWNTO 0);
VALUE :OUT T_DIGITAL);
END COMPONENT DECODER;
COMPONENT KEY_BUFFER IS
PORT( KEY :IN T_DIGITAL;
CLK :IN STD_LOGIC;
RESET :IN STD_LOGIC;
NEW_TIME:OUT T_CLOCK_TIME);
END COMPONENT KEY_BUFFER;
COMPONENT ALARM_CONTROLLER IS
PORT( KEY : IN STD_LOGIC;
ALARM_BUTTON : IN STD_LOGIC;
TIME_BUTTON : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
LOAD_NEW_A : OUT STD_LOGIC;
LOAD_NEW_C : OUT STD_LOGIC;
SHOW_NEW_TIME :OUT STD_LOGIC;
SHOW_A : OUT STD_LOGIC);
END COMPONENT ALARM_CONTROLLER;
COMPONENT ALARM_COUNTER IS
PORT(NEW_CURRENT_TIME:IN T_CLOCK_TIME;
LOAD_NEW_C: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
CURRENT_TIME:OUT T_CLOCK_TIME);
END COMPONENT ALARM_COUNTER;
COMPONENT ALARM_REG IS
PORT(NEW_ALARM_TIME: IN T_CLOCK_TIME;
LOAD_NEW_A:IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ALARM_TIME:OUT T_CLOCK_TIME);
END COMPONENT ALARM_REG;
COMPONENT DISPLAY_DRIVER IS
PORT(ALARM_TIME : IN T_CLOCK_TIME;
CURRENT_TIME :IN T_CLOCK_TIME;
NEW_TIME : IN T_CLOCK_TIME;
SHOW_NEW_TIME:IN STD_LOGIC;
SHOW_A : IN STD_LOGIC;
SOUND_ALARM : OUT STD_LOGIC;
DISPLAY: OUT T_DISPLAY);
END COMPONENT DISPLAY_DRIVER;
COMPONENT FQ_DIVIDER IS
PORT( CLK_IN: IN STD_LOGIC;
RESET: IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC );
END COMPONENT FQ_DIVIDER;
SIGNAL S0 : T_DIGITAL;
SIGNAL S1,S2,S3,S4,S5 : STD_LOGIC;
SIGNAL S6,S7,S8 : T_CLOCK_TIME;
BEGIN
U1: DECODER PORT MAP(KEYPAD, S0);
U2: KEY_BUFFER PORT MAP(S0, KEY_DOWN,RESET, S6);
U3: ALARM_CONTROLLER PORT MAP(KEY_DOWN,
ALARM_BUTTON,TIME_BUTTON,
CLK,RESET,S1,S2,S3,S4);
U4: ALARM_COUNTER PORT MAP(S6,S2,S5,RESET,S8);
U5: ALARM_REG PORT MAP(S6,S1,CLK,RESET,S7);
U6: DISPLAY_DRIVER PORT MAP(S7,S6,S8,S3,S4,
SOUND_ALARM,DISPLAY);
U7: FQ_DIVIDER PORT MAP(CLK,RESET,S5);
END ARCHIITECTURE ART;
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