alarm_clock.tan.rpt

在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                  ; To                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+--------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 44.05 MHz ( period = 22.700 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[0] ; CLK        ; CLK      ; None                        ; None                      ; 18.400 ns               ;
; N/A                                     ; 44.05 MHz ( period = 22.700 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[4] ; CLK        ; CLK      ; None                        ; None                      ; 18.500 ns               ;
; N/A                                     ; 44.25 MHz ( period = 22.600 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[3] ; CLK        ; CLK      ; None                        ; None                      ; 18.300 ns               ;
; N/A                                     ; 44.44 MHz ( period = 22.500 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[1] ; CLK        ; CLK      ; None                        ; None                      ; 18.300 ns               ;
; N/A                                     ; 44.44 MHz ( period = 22.500 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[5] ; CLK        ; CLK      ; None                        ; None                      ; 18.300 ns               ;
; N/A                                     ; 44.64 MHz ( period = 22.400 ns )                    ; KEY_BUFFER:U2|N_T[2][1]                                                               ; DISPLAY_DRIVER:U6|SEG[4] ; CLK        ; CLK      ; None                        ; None                      ; 13.200 ns               ;
; N/A                                     ; 44.64 MHz ( period = 22.400 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[6] ; CLK        ; CLK      ; None                        ; None                      ; 18.200 ns               ;
; N/A                                     ; 44.84 MHz ( period = 22.300 ns )                    ; KEY_BUFFER:U2|N_T[1][3]                                                               ; DISPLAY_DRIVER:U6|SEG[0] ; CLK        ; CLK      ; None                        ; None                      ; 13.000 ns               ;
; N/A                                     ; 45.05 MHz ( period = 22.200 ns )                    ; KEYSCAN:U1|keypress                                                                   ; DISPLAY_DRIVER:U6|SEG[2] ; CLK        ; CLK      ; None                        ; None                      ; 18.000 ns               ;
; N/A                                     ; 45.05 MHz ( period = 22.200 ns )                    ; KEY_BUFFER:U2|N_T[1][3]                                                               ; DISPLAY_DRIVER:U6|SEG[3] ; CLK        ; CLK      ; None                        ; None                      ; 12.900 ns               ;
; N/A                                     ; 45.25 MHz ( period = 22.100 ns )                    ; KEY_BUFFER:U2|N_T[1][3]                                                               ; DISPLAY_DRIVER:U6|SEG[1] ; CLK        ; CLK      ; None                        ; None                      ; 12.900 ns               ;
; N/A                                     ; 45.25 MHz ( period = 22.100 ns )                    ; KEY_BUFFER:U2|N_T[1][3]                                                               ; DISPLAY_DRIVER:U6|SEG[5] ; CLK        ; CLK      ; None                        ; None                      ; 12.900 ns               ;
; N/A                                     ; 45.25 MHz ( period = 22.100 ns )                    ; KEY_BUFFER:U2|N_T[2][1]                                                               ; DISPLAY_DRIVER:U6|SEG[6] ; CLK        ; CLK      ; None                        ; None                      ; 12.900 ns               ;
; N/A                                     ; 45.66 MHz ( period = 21.900 ns )                    ; KEY_BUFFER:U2|N_T[0][3]                                                               ; DISPLAY_DRIVER:U6|SEG[0] ; CLK        ; CLK      ; None                        ; None                      ; 12.600 ns               ;