alarm_clock.tan.qmsg

在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间

{ "Info" "ITDB_TH_RESULT" "KEYSCAN:U1\|keyvalue\[3\] KEYROW\[1\] CLK 7.500 ns register " "Info: th for register \"KEYSCAN:U1\|keyvalue\[3\]\" (data pin = \"KEYROW\[1\]\", clock pin = \"CLK\") is 7.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.500 ns) 6.500 ns FQ_DIVIDER:U7\|CLK_50hz 3 REG LC3_A5 24 " "Info: 3: + IC(3.100 ns) + CELL(0.500 ns) = 6.500 ns; Loc. = LC3_A5; Fanout = 24; REG Node = 'FQ_DIVIDER:U7\|CLK_50hz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.600 ns" { FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.000 ns) 9.400 ns KEYSCAN:U1\|keyvalue\[3\] 4 REG LC5_D27 1 " "Info: 4: + IC(2.900 ns) + CELL(0.000 ns) = 9.400 ns; Loc. = LC5_D27; Fanout = 1; REG Node = 'KEYSCAN:U1\|keyvalue\[3\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.900 ns" { FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[3] } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 31.91 % ) " "Info: Total cell delay = 3.000 ns ( 31.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns ( 68.09 % ) " "Info: Total interconnect delay = 6.400 ns ( 68.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[3] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[3] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns KEYROW\[1\] 1 PIN PIN_125 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 4; PIN Node = 'KEYROW\[1\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { KEYROW[1] } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.800 ns) 3.200 ns KEYSCAN:U1\|keyvalue\[3\] 2 REG LC5_D27 1 " "Info: 2: + IC(0.400 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC5_D27; Fanout = 1; REG Node = 'KEYSCAN:U1\|keyvalue\[3\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.200 ns" { KEYROW[1] KEYSCAN:U1|keyvalue[3] } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 87.50 % ) " "Info: Total cell delay = 2.800 ns ( 87.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 12.50 % ) " "Info: Total interconnect delay = 0.400 ns ( 12.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.200 ns" { KEYROW[1] KEYSCAN:U1|keyvalue[3] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "3.200 ns" { KEYROW[1] KEYROW[1]~out KEYSCAN:U1|keyvalue[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[3] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[3] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.200 ns" { KEYROW[1] KEYSCAN:U1|keyvalue[3] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "3.200 ns" { KEYROW[1] KEYROW[1]~out KEYSCAN:U1|keyvalue[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.800ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 21 16:24:53 2007 " "Info: Processing ended: Wed Nov 21 16:24:53 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}