📄 alarm_clock.tan.qmsg

📁 在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间
💻 QMSG
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{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "KEYSCAN:U1\|keyvalue\[0\] KEY_BUFFER:U2\|N_T\[0\]\[0\] CLK 4.7 ns " "Info: Found hold time violation between source  pin or register \"KEYSCAN:U1\|keyvalue\[0\]\" and destination pin or register \"KEY_BUFFER:U2\|N_T\[0\]\[0\]\" for clock \"CLK\" (Hold time is 4.7 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.000 ns + Largest " "Info: + Largest clock skew is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 14.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 14.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.500 ns) 6.500 ns FQ_DIVIDER:U7\|CLK_50hz 3 REG LC3_A5 24 " "Info: 3: + IC(3.100 ns) + CELL(0.500 ns) = 6.500 ns; Loc. = LC3_A5; Fanout = 24; REG Node = 'FQ_DIVIDER:U7\|CLK_50hz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.600 ns" { FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 9.900 ns KEYSCAN:U1\|keypress 4 REG LC1_D21 35 " "Info: 4: + IC(2.900 ns) + CELL(0.500 ns) = 9.900 ns; Loc. = LC1_D21; Fanout = 35; REG Node = 'KEYSCAN:U1\|keypress'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.400 ns" { FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 14.400 ns KEY_BUFFER:U2\|N_T\[0\]\[0\] 5 REG LC8_D27 6 " "Info: 5: + IC(4.500 ns) + CELL(0.000 ns) = 14.400 ns; Loc. = LC8_D27; Fanout = 6; REG Node = 'KEY_BUFFER:U2\|N_T\[0\]\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "4.500 ns" { KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 24.31 % ) " "Info: Total cell delay = 3.500 ns ( 24.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.900 ns ( 75.69 % ) " "Info: Total interconnect delay = 10.900 ns ( 75.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "14.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "14.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns 4.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 9.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.500 ns) 6.500 ns FQ_DIVIDER:U7\|CLK_50hz 3 REG LC3_A5 24 " "Info: 3: + IC(3.100 ns) + CELL(0.500 ns) = 6.500 ns; Loc. = LC3_A5; Fanout = 24; REG Node = 'FQ_DIVIDER:U7\|CLK_50hz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.600 ns" { FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.000 ns) 9.400 ns KEYSCAN:U1\|keyvalue\[0\] 4 REG LC6_D27 1 " "Info: 4: + IC(2.900 ns) + CELL(0.000 ns) = 9.400 ns; Loc. = LC6_D27; Fanout = 1; REG Node = 'KEYSCAN:U1\|keyvalue\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.900 ns" { FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 31.91 % ) " "Info: Total cell delay = 3.000 ns ( 31.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns ( 68.09 % ) " "Info: Total interconnect delay = 6.400 ns ( 68.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "14.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "14.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns 4.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.100 ns - Shortest register register " "Info: - Shortest register to register delay is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns KEYSCAN:U1\|keyvalue\[0\] 1 REG LC6_D27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_D27; Fanout = 1; REG Node = 'KEYSCAN:U1\|keyvalue\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { KEYSCAN:U1|keyvalue[0] } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 1.100 ns KEY_BUFFER:U2\|N_T\[0\]\[0\] 2 REG LC8_D27 6 " "Info: 2: + IC(0.300 ns) + CELL(0.800 ns) = 1.100 ns; Loc. = LC8_D27; Fanout = 6; REG Node = 'KEY_BUFFER:U2\|N_T\[0\]\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.100 ns" { KEYSCAN:U1|keyvalue[0] KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 72.73 % ) " "Info: Total cell delay = 0.800 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 27.27 % ) " "Info: Total interconnect delay = 0.300 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.100 ns" { KEYSCAN:U1|keyvalue[0] KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "1.100 ns" { KEYSCAN:U1|keyvalue[0] KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.300ns } { 0.000ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "14.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "14.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns 4.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keyvalue[0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.100 ns" { KEYSCAN:U1|keyvalue[0] KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "1.100 ns" { KEYSCAN:U1|keyvalue[0] KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.300ns } { 0.000ns 0.800ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "DISPLAY_DRIVER:U6\|SEG\[0\] ALARM_BUTTON CLK 15.000 ns register " "Info: tsu for register \"DISPLAY_DRIVER:U6\|SEG\[0\]\" (data pin = \"ALARM_BUTTON\", clock pin = \"CLK\") is 15.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.600 ns + Longest pin register " "Info: + Longest pin to register delay is 20.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ALARM_BUTTON 1 PIN PIN_54 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 7; PIN Node = 'ALARM_BUTTON'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { ALARM_BUTTON } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 3.900 ns ALARM_CONTROLLER:U3\|Selector4~17 2 COMB LC1_F30 3 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC1_F30; Fanout = 3; COMB Node = 'ALARM_CONTROLLER:U3\|Selector4~17'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ALARM_BUTTON ALARM_CONTROLLER:U3|Selector4~17 } "NODE_NAME" } } { "ALARM_CONTROLLER.vhd" "" { Text "E:/clock/ALARM_CONTROLLER.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 5.800 ns DISPLAY_DRIVER:U6\|comb~3677 3 COMB LC3_F30 24 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.800 ns; Loc. = LC3_F30; Fanout = 24; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3677'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ALARM_CONTROLLER:U3|Selector4~17 DISPLAY_DRIVER:U6|comb~3677 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 8.400 ns DISPLAY_DRIVER:U6\|comb~3707 4 COMB LC7_F29 1 " "Info: 4: + IC(1.200 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC7_F29; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3707'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.600 ns" { DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.600 ns) 12.100 ns DISPLAY_DRIVER:U6\|comb~3708 5 COMB LC1_F8 7 " "Info: 5: + IC(2.100 ns) + CELL(1.600 ns) = 12.100 ns; Loc. = LC1_F8; Fanout = 7; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3708'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.700 ns" { DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 14.700 ns DISPLAY_DRIVER:U6\|Mux13~3 6 COMB LC1_F7 1 " "Info: 6: + IC(1.000 ns) + CELL(1.600 ns) = 14.700 ns; Loc. = LC1_F7; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux13~3'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.600 ns" { DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.600 ns) 17.400 ns DISPLAY_DRIVER:U6\|Mux54~112 7 COMB LC4_F9 1 " "Info: 7: + IC(1.100 ns) + CELL(1.600 ns) = 17.400 ns; Loc. = LC4_F9; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux54~112'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.700 ns" { DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 19.300 ns DISPLAY_DRIVER:U6\|Mux54~113 8 COMB LC5_F9 1 " "Info: 8: + IC(0.300 ns) + CELL(1.600 ns) = 19.300 ns; Loc. = LC5_F9; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux54~113'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.900 ns" { DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 20.600 ns DISPLAY_DRIVER:U6\|SEG\[0\] 9 REG LC2_F9 1 " "Info: 9: + IC(0.300 ns) + CELL(1.000 ns) = 20.600 ns; Loc. = LC2_F9; Fanout = 1; REG Node = 'DISPLAY_DRIVER:U6\|SEG\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.300 ns" { DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns ( 67.96 % ) " "Info: Total cell delay = 14.000 ns ( 67.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns ( 32.04 % ) " "Info: Total interconnect delay = 6.600 ns ( 32.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "20.600 ns" { ALARM_BUTTON ALARM_CONTROLLER:U3|Selector4~17 DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "20.600 ns" { ALARM_BUTTON ALARM_BUTTON~out ALARM_CONTROLLER:U3|Selector4~17 DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.300ns 0.300ns 1.200ns 2.100ns 1.000ns 1.100ns 0.300ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.600ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.200 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 6.200 ns DISPLAY_DRIVER:U6\|SEG\[0\] 3 REG LC2_F9 1 " "Info: 3: + IC(3.300 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = LC2_F9; Fanout = 1; REG Node = 'DISPLAY_DRIVER:U6\|SEG\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.300 ns" { FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 40.32 % ) " "Info: Total cell delay = 2.500 ns ( 40.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 59.68 % ) " "Info: Total interconnect delay = 3.700 ns ( 59.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "6.200 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.400ns 3.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "20.600 ns" { ALARM_BUTTON ALARM_CONTROLLER:U3|Selector4~17 DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "20.600 ns" { ALARM_BUTTON ALARM_BUTTON~out ALARM_CONTROLLER:U3|Selector4~17 DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.300ns 0.300ns 1.200ns 2.100ns 1.000ns 1.100ns 0.300ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.600ns 1.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "6.200 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.400ns 3.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SOUND_ALARM KEY_BUFFER:U2\|N_T\[5\]\[0\] 32.300 ns register " "Info: tco from clock \"CLK\" to destination pin \"SOUND_ALARM\" through register \"KEY_BUFFER:U2\|N_T\[5\]\[0\]\" is 32.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 14.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.500 ns) 6.500 ns FQ_DIVIDER:U7\|CLK_50hz 3 REG LC3_A5 24 " "Info: 3: + IC(3.100 ns) + CELL(0.500 ns) = 6.500 ns; Loc. = LC3_A5; Fanout = 24; REG Node = 'FQ_DIVIDER:U7\|CLK_50hz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.600 ns" { FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 9.900 ns KEYSCAN:U1\|keypress 4 REG LC1_D21 35 " "Info: 4: + IC(2.900 ns) + CELL(0.500 ns) = 9.900 ns; Loc. = LC1_D21; Fanout = 35; REG Node = 'KEYSCAN:U1\|keypress'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.400 ns" { FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 14.400 ns KEY_BUFFER:U2\|N_T\[5\]\[0\] 5 REG LC7_E19 4 " "Info: 5: + IC(4.500 ns) + CELL(0.000 ns) = 14.400 ns; Loc. = LC7_E19; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[5\]\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "4.500 ns" { KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[5][0] } "NODE_NAME" } } { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 24.31 % ) " "Info: Total cell delay = 3.500 ns ( 24.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.900 ns ( 75.69 % ) " "Info: Total interconnect delay = 10.900 ns ( 75.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "14.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[5][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "14.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[5][0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns 4.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.400 ns + Longest register pin " "Info: + Longest register to pin delay is 17.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns KEY_BUFFER:U2\|N_T\[5\]\[0\] 1 REG LC7_E19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_E19; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[5\]\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { KEY_BUFFER:U2|N_T[5][0] } "NODE_NAME" } } { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.800 ns) 3.300 ns DISPLAY_DRIVER:U6\|CTRL~309 2 COMB LC1_F18 1 " "Info: 2: + IC(2.500 ns) + CELL(0.800 ns) = 3.300 ns; Loc. = LC1_F18; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~309'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.300 ns" { KEY_BUFFER:U2|N_T[5][0] DISPLAY_DRIVER:U6|CTRL~309 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 4.900 ns DISPLAY_DRIVER:U6\|CTRL~290 3 COMB LC2_F18 1 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 4.900 ns; Loc. = LC2_F18; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~290'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.600 ns" { DISPLAY_DRIVER:U6|CTRL~309 DISPLAY_DRIVER:U6|CTRL~290 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.600 ns) 8.300 ns DISPLAY_DRIVER:U6\|CTRL~260 4 COMB LC1_F27 1 " "Info: 4: + IC(1.800 ns) + CELL(1.600 ns) = 8.300 ns; Loc. = LC1_F27; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~260'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.400 ns" { DISPLAY_DRIVER:U6|CTRL~290 DISPLAY_DRIVER:U6|CTRL~260 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 10.200 ns DISPLAY_DRIVER:U6\|CTRL~262 5 COMB LC4_F27 1 " "Info: 5: + IC(0.300 ns) + CELL(1.600 ns) = 10.200 ns; Loc. = LC4_F27; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~262'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.900 ns" { DISPLAY_DRIVER:U6|CTRL~260 DISPLAY_DRIVER:U6|CTRL~262 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(6.300 ns) 17.400 ns SOUND_ALARM 6 PIN PIN_133 0 " "Info: 6: + IC(0.900 ns) + CELL(6.300 ns) = 17.400 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'SOUND_ALARM'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "7.200 ns" { DISPLAY_DRIVER:U6|CTRL~262 SOUND_ALARM } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.900 ns ( 68.39 % ) " "Info: Total cell delay = 11.900 ns ( 68.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 31.61 % ) " "Info: Total interconnect delay = 5.500 ns ( 31.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "17.400 ns" { KEY_BUFFER:U2|N_T[5][0] DISPLAY_DRIVER:U6|CTRL~309 DISPLAY_DRIVER:U6|CTRL~290 DISPLAY_DRIVER:U6|CTRL~260 DISPLAY_DRIVER:U6|CTRL~262 SOUND_ALARM } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "17.400 ns" { KEY_BUFFER:U2|N_T[5][0] DISPLAY_DRIVER:U6|CTRL~309 DISPLAY_DRIVER:U6|CTRL~290 DISPLAY_DRIVER:U6|CTRL~260 DISPLAY_DRIVER:U6|CTRL~262 SOUND_ALARM } { 0.000ns 2.500ns 0.000ns 1.800ns 0.300ns 0.900ns } { 0.000ns 0.800ns 1.600ns 1.600ns 1.600ns 6.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "14.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[5][0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "14.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress KEY_BUFFER:U2|N_T[5][0] } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns 4.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "17.400 ns" { KEY_BUFFER:U2|N_T[5][0] DISPLAY_DRIVER:U6|CTRL~309 DISPLAY_DRIVER:U6|CTRL~290 DISPLAY_DRIVER:U6|CTRL~260 DISPLAY_DRIVER:U6|CTRL~262 SOUND_ALARM } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "17.400 ns" { KEY_BUFFER:U2|N_T[5][0] DISPLAY_DRIVER:U6|CTRL~309 DISPLAY_DRIVER:U6|CTRL~290 DISPLAY_DRIVER:U6|CTRL~260 DISPLAY_DRIVER:U6|CTRL~262 SOUND_ALARM } { 0.000ns 2.500ns 0.000ns 1.800ns 0.300ns 0.900ns } { 0.000ns 0.800ns 1.600ns 1.600ns 1.600ns 6.300ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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