alarm_clock.tan.qmsg

在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FQ_DIVIDER:U7\|CLK_1hz " "Info: Detected ripple clock \"FQ_DIVIDER:U7\|CLK_1hz\" as buffer" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 11 -1 0 } } { "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" "" { Assignment "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" 1 { { 0 "FQ_DIVIDER:U7\|CLK_1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "KEYSCAN:U1\|keypress " "Info: Detected ripple clock \"KEYSCAN:U1\|keypress\" as buffer" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 13 -1 0 } } { "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" "" { Assignment "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" 1 { { 0 "KEYSCAN:U1\|keypress" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FQ_DIVIDER:U7\|CLK_1Khz " "Info: Detected ripple clock \"FQ_DIVIDER:U7\|CLK_1Khz\" as buffer" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } } { "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" "" { Assignment "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" 1 { { 0 "FQ_DIVIDER:U7\|CLK_1Khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FQ_DIVIDER:U7\|CLK_50hz " "Info: Detected ripple clock \"FQ_DIVIDER:U7\|CLK_50hz\" as buffer" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 10 -1 0 } } { "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" "" { Assignment "d:/quartus-iiss/anzhuang/win/Assignment Editor.qase" 1 { { 0 "FQ_DIVIDER:U7\|CLK_50hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register KEYSCAN:U1\|keypress register DISPLAY_DRIVER:U6\|SEG\[0\] 44.05 MHz 22.7 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 44.05 MHz between source register \"KEYSCAN:U1\|keypress\" and destination register \"DISPLAY_DRIVER:U6\|SEG\[0\]\" (period= 22.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.400 ns + Longest register register " "Info: + Longest register to register delay is 18.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns KEYSCAN:U1\|keypress 1 REG LC1_D21 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D21; Fanout = 35; REG Node = 'KEYSCAN:U1\|keypress'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { KEYSCAN:U1|keypress } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.600 ns) 3.600 ns DISPLAY_DRIVER:U6\|comb~3677 2 COMB LC3_F30 24 " "Info: 2: + IC(2.000 ns) + CELL(1.600 ns) = 3.600 ns; Loc. = LC3_F30; Fanout = 24; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3677'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.600 ns" { KEYSCAN:U1|keypress DISPLAY_DRIVER:U6|comb~3677 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 6.200 ns DISPLAY_DRIVER:U6\|comb~3707 3 COMB LC7_F29 1 " "Info: 3: + IC(1.200 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC7_F29; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3707'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.600 ns" { DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.600 ns) 9.900 ns DISPLAY_DRIVER:U6\|comb~3708 4 COMB LC1_F8 7 " "Info: 4: + IC(2.100 ns) + CELL(1.600 ns) = 9.900 ns; Loc. = LC1_F8; Fanout = 7; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3708'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.700 ns" { DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 12.500 ns DISPLAY_DRIVER:U6\|Mux13~3 5 COMB LC1_F7 1 " "Info: 5: + IC(1.000 ns) + CELL(1.600 ns) = 12.500 ns; Loc. = LC1_F7; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux13~3'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.600 ns" { DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.600 ns) 15.200 ns DISPLAY_DRIVER:U6\|Mux54~112 6 COMB LC4_F9 1 " "Info: 6: + IC(1.100 ns) + CELL(1.600 ns) = 15.200 ns; Loc. = LC4_F9; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux54~112'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.700 ns" { DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 17.100 ns DISPLAY_DRIVER:U6\|Mux54~113 7 COMB LC5_F9 1 " "Info: 7: + IC(0.300 ns) + CELL(1.600 ns) = 17.100 ns; Loc. = LC5_F9; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux54~113'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.900 ns" { DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 18.400 ns DISPLAY_DRIVER:U6\|SEG\[0\] 8 REG LC2_F9 1 " "Info: 8: + IC(0.300 ns) + CELL(1.000 ns) = 18.400 ns; Loc. = LC2_F9; Fanout = 1; REG Node = 'DISPLAY_DRIVER:U6\|SEG\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "1.300 ns" { DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.400 ns ( 56.52 % ) " "Info: Total cell delay = 10.400 ns ( 56.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns ( 43.48 % ) " "Info: Total interconnect delay = 8.000 ns ( 43.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "18.400 ns" { KEYSCAN:U1|keypress DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "18.400 ns" { KEYSCAN:U1|keypress DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 2.000ns 1.200ns 2.100ns 1.000ns 1.100ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.600ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.200 ns - Smallest " "Info: - Smallest clock skew is -3.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.200 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 6.200 ns DISPLAY_DRIVER:U6\|SEG\[0\] 3 REG LC2_F9 1 " "Info: 3: + IC(3.300 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = LC2_F9; Fanout = 1; REG Node = 'DISPLAY_DRIVER:U6\|SEG\[0\]'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.300 ns" { FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 40.32 % ) " "Info: Total cell delay = 2.500 ns ( 40.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 59.68 % ) " "Info: Total interconnect delay = 3.700 ns ( 59.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "6.200 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.400ns 3.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 9.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 83; CLK Node = 'CLK'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FQ_DIVIDER:U7\|CLK_1Khz 2 REG LC4_C31 27 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC4_C31; Fanout = 27; REG Node = 'FQ_DIVIDER:U7\|CLK_1Khz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.500 ns) 6.500 ns FQ_DIVIDER:U7\|CLK_50hz 3 REG LC3_A5 24 " "Info: 3: + IC(3.100 ns) + CELL(0.500 ns) = 6.500 ns; Loc. = LC3_A5; Fanout = 24; REG Node = 'FQ_DIVIDER:U7\|CLK_50hz'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "3.600 ns" { FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.000 ns) 9.400 ns KEYSCAN:U1\|keypress 4 REG LC1_D21 35 " "Info: 4: + IC(2.900 ns) + CELL(0.000 ns) = 9.400 ns; Loc. = LC1_D21; Fanout = 35; REG Node = 'KEYSCAN:U1\|keypress'" {  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "2.900 ns" { FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } "NODE_NAME" } } { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 31.91 % ) " "Info: Total cell delay = 3.000 ns ( 31.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns ( 68.09 % ) " "Info: Total interconnect delay = 6.400 ns ( 68.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "6.200 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.400ns 3.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "18.400 ns" { KEYSCAN:U1|keypress DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "18.400 ns" { KEYSCAN:U1|keypress DISPLAY_DRIVER:U6|comb~3677 DISPLAY_DRIVER:U6|comb~3707 DISPLAY_DRIVER:U6|comb~3708 DISPLAY_DRIVER:U6|Mux13~3 DISPLAY_DRIVER:U6|Mux54~112 DISPLAY_DRIVER:U6|Mux54~113 DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 2.000ns 1.200ns 2.100ns 1.000ns 1.100ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.600ns 1.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "6.200 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz DISPLAY_DRIVER:U6|SEG[0] } { 0.000ns 0.000ns 0.400ns 3.300ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus-iiss/anzhuang/win/TimingClosureFloorplan.fld" "" "9.400 ns" { CLK FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } "NODE_NAME" } } { "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus-iiss/anzhuang/win/Technology_Viewer.qrui" "9.400 ns" { CLK CLK~out FQ_DIVIDER:U7|CLK_1Khz FQ_DIVIDER:U7|CLK_50hz KEYSCAN:U1|keypress } { 0.000ns 0.000ns 0.400ns 3.100ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}