alarm_clock.map.qmsg

在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 21 16:24:15 2007 " "Info: Processing started: Wed Nov 21 16:24:15 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALARM_CLOCK -c ALARM_CLOCK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ALARM_CLOCK -c ALARM_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_CLOCK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_CLOCK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_CLOCK-ART " "Info: Found design unit 1: ALARM_CLOCK-ART" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_CLOCK " "Info: Found entity 1: ALARM_CLOCK" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/clock/ALARM_CLOCK.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_CONTROLLER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_CONTROLLER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_CONTROLLER-ART " "Info: Found design unit 1: ALARM_CONTROLLER-ART" {  } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/clock/ALARM_CONTROLLER.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_CONTROLLER " "Info: Found entity 1: ALARM_CONTROLLER" {  } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/clock/ALARM_CONTROLLER.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_COUNTER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_COUNTER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_COUNTER-ART " "Info: Found design unit 1: ALARM_COUNTER-ART" {  } { { "ALARM_COUNTER.vhd" "" { Text "E:/clock/ALARM_COUNTER.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_COUNTER " "Info: Found entity 1: ALARM_COUNTER" {  } { { "ALARM_COUNTER.vhd" "" { Text "E:/clock/ALARM_COUNTER.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALARM_REG.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALARM_REG.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_REG-ART " "Info: Found design unit 1: ALARM_REG-ART" {  } { { "ALARM_REG.vhd" "" { Text "E:/clock/ALARM_REG.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_REG " "Info: Found entity 1: ALARM_REG" {  } { { "ALARM_REG.vhd" "" { Text "E:/clock/ALARM_REG.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DISPLAY_DRIVER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DISPLAY_DRIVER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DISPLAY_DRIVER-ART " "Info: Found design unit 1: DISPLAY_DRIVER-ART" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY_DRIVER " "Info: Found entity 1: DISPLAY_DRIVER" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FQ_DIVIDER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FQ_DIVIDER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FQ_DIVIDER-ART " "Info: Found design unit 1: FQ_DIVIDER-ART" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FQ_DIVIDER " "Info: Found entity 1: FQ_DIVIDER" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/clock/FQ_DIVIDER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "KEY_BUFFER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file KEY_BUFFER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 KEY_BUFFER-ART " "Info: Found design unit 1: KEY_BUFFER-ART" {  } { { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 KEY_BUFFER " "Info: Found entity 1: KEY_BUFFER" {  } { { "KEY_BUFFER.vhd" "" { Text "E:/clock/KEY_BUFFER.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "P_ALARM.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file P_ALARM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 P_ALARM " "Info: Found design unit 1: P_ALARM" {  } { { "P_ALARM.vhd" "" { Text "E:/clock/P_ALARM.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "KEYSCAN.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file KEYSCAN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 KEYSCAN-ART " "Info: Found design unit 1: KEYSCAN-ART" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 KEYSCAN " "Info: Found entity 1: KEYSCAN" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ALARM_CLOCK " "Info: Elaborating entity \"ALARM_CLOCK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KEYSCAN KEYSCAN:U1 " "Info: Elaborating entity \"KEYSCAN\" for hierarchy \"KEYSCAN:U1\"" {  } { { "ALARM_CLOCK.vhd" "U1" { Text "E:/clock/ALARM_CLOCK.vhd" 93 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "row KEYSCAN.vhd(55) " "Warning (10492): VHDL Process Statement warning at KEYSCAN.vhd(55): signal \"row\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 55 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "scanin KEYSCAN.vhd(55) " "Warning (10492): VHDL Process Statement warning at KEYSCAN.vhd(55): signal \"scanin\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "KEYSCAN.vhd" "" { Text "E:/clock/KEYSCAN.vhd" 55 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KEY_BUFFER KEY_BUFFER:U2 " "Info: Elaborating entity \"KEY_BUFFER\" for hierarchy \"KEY_BUFFER:U2\"" {  } { { "ALARM_CLOCK.vhd" "U2" { Text "E:/clock/ALARM_CLOCK.vhd" 99 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALARM_CONTROLLER ALARM_CONTROLLER:U3 " "Info: Elaborating entity \"ALARM_CONTROLLER\" for hierarchy \"ALARM_CONTROLLER:U3\"" {  } { { "ALARM_CLOCK.vhd" "U3" { Text "E:/clock/ALARM_CLOCK.vhd" 100 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALARM_COUNTER ALARM_COUNTER:U4 " "Info: Elaborating entity \"ALARM_COUNTER\" for hierarchy \"ALARM_COUNTER:U4\"" {  } { { "ALARM_CLOCK.vhd" "U4" { Text "E:/clock/ALARM_CLOCK.vhd" 103 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALARM_REG ALARM_REG:U5 " "Info: Elaborating entity \"ALARM_REG\" for hierarchy \"ALARM_REG:U5\"" {  } { { "ALARM_CLOCK.vhd" "U5" { Text "E:/clock/ALARM_CLOCK.vhd" 104 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DISPLAY_DRIVER DISPLAY_DRIVER:U6 " "Info: Elaborating entity \"DISPLAY_DRIVER\" for hierarchy \"DISPLAY_DRIVER:U6\"" {  } { { "ALARM_CLOCK.vhd" "U6" { Text "E:/clock/ALARM_CLOCK.vhd" 105 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DISPLAY_TIME DISPLAY_DRIVER.vhd(21) " "Warning (10631): VHDL Process Statement warning at DISPLAY_DRIVER.vhd(21): inferring latch(es) for signal or variable \"DISPLAY_TIME\", which holds its previous value in one or more paths through the process" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 21 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DISPLAY_TIME\[0\]\[0\] DISPLAY_DRIVER.vhd(21) " "Info (10041): Verilog HDL or VHDL info at DISPLAY_DRIVER.vhd(21): inferred latch for \"DISPLAY_TIME\[0\]\[0\]\"" {  } { { "DISPLAY_DRIVER.vhd" "" { Text "E:/clock/DISPLAY_DRIVER.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}