fq_divider.vhd

在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY FQ_DIVIDER IS
    PORT( CLK_40Mhz: IN  STD_LOGIC;
          RESET:     IN  STD_LOGIC;
          --CLK_1Khz:  OUT STD_LOGIC;
          CLK_1Khz:  BUFFER STD_LOGIC;
          --CLK_50hz:  OUT STD_LOGIC;  --20ms
          CLK_50hz:  BUFFER STD_LOGIC;  --20ms
          CLK_1hz:   OUT STD_LOGIC );--1s
END ENTITY FQ_DIVIDER;
--------------------------------------------------
ARCHITECTURE ART OF FQ_DIVIDER IS
    CONSTANT DIVIDE_PERIOD :integer := 40000;
    CONSTANT DIVIDE_PERIOD1 :integer := 20;
    CONSTANT DIVIDE_PERIOD2 :integer := 50;
BEGIN
----------------------------------------------
    DIVIDE_CLK:PROCESS(clk_40Mhz) IS
        VARIABLE CNT :integer range 0 to 65535;
    BEGIN
        IF (RESET = '1') THEN
            CNT := 0; CLK_1Khz <= '0';
        ELSIF RISING_EDGE(clk_40Mhz) THEN
            IF (CNT < (DIVIDE_PERIOD/2)) THEN
                clk_1khz <= '1';
                CNT := CNT + 1;
            ELSIF (CNT < (DIVIDE_PERIOD-1)) THEN
                clk_1Khz <= '0';
                CNT := CNT + 1;
            ELSE
                CNT := 0;
            END IF;
        END IF;
    END PROCESS  DIVIDE_CLK;
-----------------------------------------------------
    DIVIDE_CLK1:PROCESS(clk_1Khz) IS
        VARIABLE CNT :integer range 0 to 32;
    BEGIN
        IF (RESET = '1') THEN
            CNT := 0; CLK_50hz <= '0';
        ELSIF RISING_EDGE(clk_1Khz) THEN
            IF (CNT < (DIVIDE_PERIOD1/2)) THEN
                clk_50hz <= '1';
                CNT := CNT + 1;
            ELSIF (CNT < (DIVIDE_PERIOD1-1)) THEN
                clk_50hz <= '0';
                CNT := CNT + 1;
            ELSE
                CNT := 0;
            END IF;
        END IF;
    END PROCESS  DIVIDE_CLK1;
-------------------------------------------------
    DIVIDE_CLK2:PROCESS(clk_50hz) IS
        VARIABLE CNT :integer range 0 to 64;
    BEGIN
        IF (RESET = '1') THEN
            CNT := 0; CLK_1hz <= '0';
        ELSIF RISING_EDGE(clk_50hz) THEN
            IF (CNT < (DIVIDE_PERIOD2/2)) THEN
                clk_1hz <= '1';
                CNT := CNT + 1;
            ELSIF (CNT < (DIVIDE_PERIOD2-1)) THEN
                clk_1hz <= '0';
                CNT := CNT + 1;
            ELSE
                CNT := 0;
            END IF;
        END IF;
    END PROCESS  DIVIDE_CLK2;
----------------------------------
END ARCHITECTURE ART;