📄 alarm_clock.map.rpt
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Analysis & Synthesis report for ALARM_CLOCK
Wed Nov 21 16:24:22 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. State Machine - |ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE
8. General Register Statistics
9. Source assignments for KEY_BUFFER:U2
10. Source assignments for ALARM_CONTROLLER:U3
11. Source assignments for ALARM_COUNTER:U4
12. Source assignments for DISPLAY_DRIVER:U6
13. Source assignments for FQ_DIVIDER:U7
14. Parameter Settings for Inferred Entity Instance: ALARM_COUNTER:U4|lpm_counter:I_CURRENT_TIME_rtl_0
15. Parameter Settings for Inferred Entity Instance: ALARM_COUNTER:U4|lpm_counter:I_CURRENT_TIME_rtl_1
16. Parameter Settings for Inferred Entity Instance: ALARM_COUNTER:U4|lpm_counter:I_CURRENT_TIME_rtl_2
17. Parameter Settings for Inferred Entity Instance: ALARM_COUNTER:U4|lpm_counter:I_CURRENT_TIME_rtl_3
18. Parameter Settings for Inferred Entity Instance: ALARM_COUNTER:U4|lpm_counter:I_CURRENT_TIME_rtl_4
19. Parameter Settings for Inferred Entity Instance: ALARM_CONTROLLER:U3|lpm_counter:COUNTER_K_rtl_5
20. Parameter Settings for Inferred Entity Instance: ALARM_CONTROLLER:U3|lpm_counter:COUNTER_A_rtl_6
21. Parameter Settings for Inferred Entity Instance: FQ_DIVIDER:U7|lpm_counter:\DIVIDE_CLK1:CNT[0]_rtl_7
22. Parameter Settings for Inferred Entity Instance: FQ_DIVIDER:U7|lpm_counter:\DIVIDE_CLK:CNT[0]_rtl_8
23. Parameter Settings for Inferred Entity Instance: FQ_DIVIDER:U7|lpm_counter:\DIVIDE_CLK2:CNT[0]_rtl_9
24. Parameter Settings for Inferred Entity Instance: ALARM_COUNTER:U4|lpm_add_sub:Add4
25. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Nov 21 16:24:22 2007 ;
; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name ; ALARM_CLOCK ;
; Top-level Entity Name ; ALARM_CLOCK ;
; Family ; ACEX1K ;
; Total logic elements ; 363 ;
; Total pins ; 26 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------+---------------+---------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+---------------+---------------+
; Device ; EP1K30TC144-3 ; ;
; Top-level entity name ; ALARM_CLOCK ; ALARM_CLOCK ;
; Family name ; ACEX1K ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+------------------------------------------------------------+---------------+---------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------------------+
; ALARM_CLOCK.vhd ; yes ; User VHDL File ; E:/clock/ALARM_CLOCK.vhd ;
; ALARM_CONTROLLER.vhd ; yes ; User VHDL File ; E:/clock/ALARM_CONTROLLER.vhd ;
; ALARM_COUNTER.vhd ; yes ; User VHDL File ; E:/clock/ALARM_COUNTER.vhd ;
; ALARM_REG.vhd ; yes ; User VHDL File ; E:/clock/ALARM_REG.vhd ;
; DISPLAY_DRIVER.vhd ; yes ; User VHDL File ; E:/clock/DISPLAY_DRIVER.vhd ;
; FQ_DIVIDER.vhd ; yes ; User VHDL File ; E:/clock/FQ_DIVIDER.vhd ;
; KEY_BUFFER.vhd ; yes ; User VHDL File ; E:/clock/KEY_BUFFER.vhd ;
; P_ALARM.vhd ; yes ; User VHDL File ; E:/clock/P_ALARM.vhd ;
; KEYSCAN.vhd ; yes ; User VHDL File ; E:/clock/KEYSCAN.vhd ;
; lpm_counter.tdf ; yes ; Megafunction ; d:/quartus-iiss/anzhuang/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Other ; d:/quartus-iiss/anzhuang/libraries/megafunctions/alt_synch_counter_f.inc ;
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