mem_interface_top_tb.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: top_tb.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-4
//Purpose:
//    This is the simulation test bench for the 64-bit interface with CL=4, BL=4
//Revision History:
//    Generated by MIG 1.x
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps

module top_tb;

reg        sys_clk_in;
reg        sys_clk_in_L;
reg        sys_rst_in;
reg        clk200_in_L;
reg        clk200_in;

wire [63:0]   ddr2_dq;
wire [7:0]    ddr2_dqs;
wire [7:0]    ddr2_dqs_n;
wire [7:0]   ddr2_dm;
wire [2:0]   ddr2_clk;
wire [2:0]   ddr2_clk_n;
wire [13:0]  ddr2_address;
wire [1:0]   ddr2_ba;     
wire         ddr2_ras_L;  
wire         ddr2_cas_L;  
wire         ddr2_we_L;   
wire [1:0]   ddr2_cs_L;
wire [1:0]   ddr2_cke;
wire [1:0]   ddr2_odt;    
wire         error;
wire         rdimm_rst;
//wire         clkdiv0;
//wire         clkdiv90;
//wire         clkdiv270;

mem_tb_top uut (
                .SYS_CLK_P(sys_clk_in),
                .SYS_CLK_N(sys_clk_in_L),
                .CLK200_P(clk200_in),
                .CLK200_N(clk200_in_L),
                .SYS_RESET_IN(sys_rst_in),
                .cntrl0_DDR2_DQ(ddr2_dq),
                .cntrl0_DDR2_DQS(ddr2_dqs),
                .cntrl0_DDR2_DQS_N(ddr2_dqs_n),
                .cntrl0_DDR2_A(ddr2_address),
                .cntrl0_DDR2_BA(ddr2_ba),
                .cntrl0_DDR2_RAS_N(ddr2_ras_L),
                .cntrl0_DDR2_CAS_N(ddr2_cas_L),
                .cntrl0_DDR2_WE_N(ddr2_we_L),
                .cntrl0_DDR2_CS_N(ddr2_cs_L),
                .cntrl0_DDR2_ODT(ddr2_odt),
                .cntrl0_DDR2_CKE(ddr2_cke),
                .cntrl0_DDR2_DM(ddr2_dm),
                .cntrl0_ERROR(error),
                .cntrl0_DDR2_CK(ddr2_clk),
                .cntrl0_DDR2_CK_N(ddr2_clk_n),
                .cntrl0_DDR2_RESET_N(rdimm_rst)
         );
         

ddr2 mt47h32m16bt0 (
                    .CLK(ddr2_clk[0]),
                    .CLK_N(ddr2_clk_n[0]),
                    .CKE(ddr2_cke[0]),
                    .CS_N(ddr2_cs_L[0]),
                    .RAS_N(ddr2_ras_L),
                    .CAS_N(ddr2_cas_L),
                    .WE_N(ddr2_we_L),
                    .DM_RDQS(ddr2_dm[1:0]),
                    .BA(ddr2_ba),
                    .ADDR(ddr2_address[12:0]),
                    .DQ(ddr2_dq[15:0]),
                    .DQS(ddr2_dqs[1:0]),
                    .DQS_N(ddr2_dqs_n[1:0]),
                    .RDQS_N(),
                    .ODT(ddr2_odt[0])
                    );
                    
ddr2 mt47h32m16bt1 (
                    .CLK(ddr2_clk[1]),
                    .CLK_N(ddr2_clk_n[1]),
                    .CKE(ddr2_cke[0]),
                    .CS_N(ddr2_cs_L[0]),
                    .RAS_N(ddr2_ras_L),
                    .CAS_N(ddr2_cas_L),
                    .WE_N(ddr2_we_L),
                    .DM_RDQS(ddr2_dm[3:2]),
                    .BA(ddr2_ba),
                    .ADDR(ddr2_address[12:0]),
                    .DQ(ddr2_dq[31:16]),
                    .DQS(ddr2_dqs[3:2]),
                    .DQS_N(ddr2_dqs_n[3:2]),
                    .RDQS_N(),
                    .ODT(ddr2_odt[0])
                    );
                    
ddr2 mt47h32m16bt2 (
                    .CLK(ddr2_clk[2]),
                    .CLK_N(ddr2_clk_n[2]),
                    .CKE(ddr2_cke[1]),
                    .CS_N(ddr2_cs_L[1]),
                    .RAS_N(ddr2_ras_L),
                    .CAS_N(ddr2_cas_L),
                    .WE_N(ddr2_we_L),
                    .DM_RDQS(ddr2_dm[5:4]),
                    .BA(ddr2_ba),
                    .ADDR(ddr2_address[12:0]),
                    .DQ(ddr2_dq[47:32]),
                    .DQS(ddr2_dqs[5:4]),
                    .DQS_N(ddr2_dqs_n[5:4]),
                    .RDQS_N(),
                    .ODT(ddr2_odt[0])
                    );
                    
ddr2 mt47h32m16bt3 (
                    .CLK(ddr2_clk[2]),
                    .CLK_N(ddr2_clk_n[2]),
                    .CKE(ddr2_cke[1]),
                    .CS_N(ddr2_cs_L[1]),
                    .RAS_N(ddr2_ras_L),
                    .CAS_N(ddr2_cas_L),
                    .WE_N(ddr2_we_L),
                    .DM_RDQS(ddr2_dm[7:6]),
                    .BA(ddr2_ba),
                    .ADDR(ddr2_address[12:0]),
                    .DQ(ddr2_dq[63:48]),
                    .DQS(ddr2_dqs[7:6]),
                    .DQS_N(ddr2_dqs_n[7:6]),
                    .RDQS_N(),
                    .ODT(ddr2_odt[0])
                    );                                                            


initial
begin
  sys_clk_in   = 1'b0;
  sys_clk_in_L = 1'b1;
  clk200_in_L  = 1'b1;
  clk200_in    = 1'b0;
  sys_rst_in   = 1'b0;
  #120 
  sys_rst_in = 1'b1;
end
  
                    
always
 sys_clk_in = #1.875 ~sys_clk_in; // 267 MHz input clock for memory interface
 
always
 sys_clk_in_L = #1.875 ~sys_clk_in_L; // 267 MHz input clock for memory interface

always
 clk200_in = #2.5 ~clk200_in; // 200 MHz input clock for IDELAYCTRL
 
always
 clk200_in_L = #2.5 ~clk200_in_L; // 200 MHz input clock for IDELAYCTRL  
 
 
endmodule