mem_phy_io.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////



module mem_phy_io (
   input          CLK,
   input          CLK90,
//   input          CAL_CLK,
   input          RESET0,
   input          RESET90,   
   input          dqs_rst,
   input          dqs_en,
   input          ctrl_rden,
   input          idelay_ctrl_rdy,
   input          phy_init_rden,
   input          phy_init_initialization_done,
   input          phy_init_st1_read,
   input          phy_init_st2_read,


   output [43:0]   test_bus,				   
   output          first_calib_done,
   output          second_calib_done,
   output          [`data_strobe_width-1:0] phy_calib_rden,
				      
   input [`data_width-1:0]   wr_data_rise,
   input [`data_width-1:0]   wr_data_fall,
   input          wr_en,
   output[`data_width-1:0]   rd_data_rise,
   output[`data_width-1:0]   rd_data_fall,
   input [`data_mask_width-1:0]    mask_data_rise,
   input [`data_mask_width-1:0]    mask_data_fall,

   inout [`data_width-1:0]   DDR_DQ,
   inout [`data_strobe_width-1:0]   DDR_DQS,
   inout [`data_strobe_width-1:0]   DDR_DQS_L,
   output [`data_mask_width-1:0]   DDR_DM

                     );

  



   wire  [`data_strobe_width-1:0]dqs_idelay_inc;
   wire  [`data_strobe_width-1:0]dqs_idelay_ce;
   wire  [`data_strobe_width-1:0]dqs_idelay_rst;
   wire  [`data_width-1:0]dq_idelay_inc;
   wire  [`data_width-1:0]dq_idelay_ce;
   wire  [`data_width-1:0]dq_idelay_rst; 
   wire  [`data_strobe_width-1:0] dqs_delayed; 
  
    


   mem_phy_calib mem_phy_calib0(
		       .reset90 (RESET90),
		       .phy_init_rden(phy_init_rden),
		       .phy_init_initialization_done(phy_init_initialization_done),
		       .phy_init_st1_read(phy_init_st1_read),
		       .phy_init_st2_read(phy_init_st2_read),
		       .test_bus(test_bus),
		       .ctrl_rden(ctrl_rden),
		       .clk90(CLK90),
		       .clk0(CLK),
		       .reset0(RESET),
		       .idelay_ctrl_rdy(idelay_ctrl_rdy),
		       .first_calib_done(first_calib_done),
		       .second_calib_done(second_calib_done),
		       .phy_calib_rden(phy_calib_rden),
		       .capture_data({rd_data_rise, rd_data_fall}),
		       .phy_calib_dq_dlyinc(dq_idelay_inc),
		       .phy_calib_dq_dlyce(dq_idelay_ce),
		       .phy_calib_dq_dlyrst(dq_idelay_rst),
		       .phy_calib_dqs_dlyinc(dqs_idelay_inc),
		       .phy_calib_dqs_dlyce(dqs_idelay_ce),
		       .phy_calib_dqs_dlyrst(dqs_idelay_rst));
   
   
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// DQS instances
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

genvar dqs_i;
generate
   for(dqs_i= 0; dqs_i < `data_strobe_width; dqs_i = dqs_i+1)
     begin:dqs_inst
           mem_phy_dqs_iob dqs(
                        .CLK	      (CLK),
                        .RESET        (RESET),
			.CLK90        (CLK90),
	                .DLYINC	      (dqs_idelay_inc[dqs_i]), 
	                .DLYCE	      (dqs_idelay_ce[dqs_i]),  
	                .DLYRST	      (dqs_idelay_rst[dqs_i]),
	                .CTRL_DQS_RST (dqs_rst),
	                .CTRL_DQS_EN  (dqs_en),
	                .DDR_DQS	  (DDR_DQS[dqs_i]),
	                .DDR_DQS_L	  (DDR_DQS_L[dqs_i]),
	                .DQS_RISE     (dqs_delayed[dqs_i])
                 ); 

     end // block: dq_inst
   endgenerate
 


///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//// DM instances
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

genvar dm_i;
generate
   for(dm_i= 0; dm_i < `data_mask_width; dm_i = dm_i+1)
     begin:dm_inst
	mem_phy_dm_iob
	  		 dm(
                        .CLK90		(CLK90),
	                .MASK_DATA_RISE(mask_data_rise[dm_i]),
	                .MASK_DATA_FALL(mask_data_fall[dm_i]),
	                .DDR_DM		(DDR_DM[dm_i])
                   );

     end // block: dq_inst
   endgenerate
                   
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//DQ_IOB4 instances
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

genvar dq_i;
generate
   for(dq_i= 0; dq_i < `data_width; dq_i = dq_i+1)
     begin:dq_inst
	mem_phy_dq_iob
                   dq(
                      .CLK		       (CLK),
                      .CLK90		      (CLK90),
		      .DQS                 (dqs_delayed[dq_i/8]),
                      .RESET		   (RESET90),
                      .DATA_DLYINC	   (dq_idelay_inc[dq_i]),
                      .DATA_DLYCE	   (dq_idelay_ce[dq_i]),
                      .DATA_DLYRST	   (dq_idelay_rst[dq_i]),
                      .WRITE_DATA_RISE (wr_data_rise[dq_i]),
                      .WRITE_DATA_FALL (wr_data_fall[dq_i]),
                      .CTRL_WREN	   (wr_en),
                      .DDR_DQ		   (DDR_DQ[dq_i]),
                      .READ_DATA_RISE  (rd_data_rise[dq_i]),
                      .READ_DATA_FALL  (rd_data_fall[dq_i])
                    );
     end // block: dq_inst
   endgenerate
   

                         
endmodule