mem_tb_top.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns/100ps


module mem_tb_top(
input  SYS_CLK_P,
input  SYS_CLK_N,
input  CLK200_P,
input  CLK200_N,
input  SYS_RESET_IN,
		  
inout [63:0] cntrl0_DDR2_DQ,
inout [7:0] cntrl0_DDR2_DQS,
inout [7:0] cntrl0_DDR2_DQS_N,
		  
output [13:0] cntrl0_DDR2_A,
output [1:0] cntrl0_DDR2_BA,
output  cntrl0_DDR2_RAS_N,
output  cntrl0_DDR2_CAS_N,
output  cntrl0_DDR2_WE_N,
output [1:0] cntrl0_DDR2_CS_N,
output [1:0] cntrl0_DDR2_ODT,
output [1:0] cntrl0_DDR2_CKE,
output [7:0] cntrl0_DDR2_DM,
output  cntrl0_ERROR,
output [2:0] cntrl0_DDR2_CK,
output [2:0] cntrl0_DDR2_CK_N,
output cntrl0_DDR2_RESET_N
         );           



wire clk_0;                              
wire clk_90;                            
wire clk_200;        
                   
                     
wire sys_rst;
wire sys_rst90;
wire sys_rst200;
wire [35:0]   app_af_addr;
wire          app_af_wren;
wire [(`data_width*2)-1:0]app_wr_df_data;
wire [(`data_mask_width*2)-1:0]app_mask_df_data;
wire          app_wr_df_wren;
wire          wr_df_almost_full;
wire          rd_data_valid;
wire [(`data_width*2)-1:0]  rd_data_fifo_out;
wire [2:0]    burst_length;
   wire       phy_init_initialization_done;
wire [`data_width-1:0] rise_data_clk0_test;
wire [`data_width-1:0] fall_data_clk0_test;
wire test_ras_n;
wire test_cas_n;
wire test_we_n;
wire [43:0] test_bus;
   
assign cntrl0_DDR2_RESET_N = 1'b1;

mem_top     mem_top(

.DDR2_DQ	(cntrl0_DDR2_DQ),
.DDR2_A	        (cntrl0_DDR2_A),
.DDR2_BA	(cntrl0_DDR2_BA),
.DDR2_RAS_N	(cntrl0_DDR2_RAS_N),
.DDR2_CAS_N	(cntrl0_DDR2_CAS_N),
.DDR2_WE_N	(cntrl0_DDR2_WE_N),
.test_ras_n     (test_ras_n),
.test_cas_n     (test_cas_n),
.test_we_n      (test_we_n),
.DDR2_CS_N	(cntrl0_DDR2_CS_N),
.DDR2_ODT	(cntrl0_DDR2_ODT),
.DDR2_CKE	(cntrl0_DDR2_CKE),
.DDR2_DM	(cntrl0_DDR2_DM),
.DDR2_DQS	(cntrl0_DDR2_DQS),
.DDR2_DQS_N	(cntrl0_DDR2_DQS_N),
.rise_data_clk0 (rise_data_clk0_test),
.fall_data_clk0 (fall_data_clk0_test),
		    
                   .phy_init_initialization_done(phy_init_initialization_done),
                   .WDF_ALMOST_FULL(wr_df_almost_full),
                   .AF_ALMOST_FULL (af_almost_full),
                   .BURST_LENGTH(burst_length),
                   .READ_DATA_VALID(rd_data_valid),
                   .READ_DATA_FIFO_OUT(rd_data_fifo_out),
                   .APP_AF_ADDR(app_af_addr),
                   .APP_AF_WREN(app_af_wren),
                   .APP_WDF_DATA(app_wr_df_data),
                   .APP_MASK_DATA(app_mask_df_data),
                   .APP_WDF_WREN(app_wr_df_wren),

.clk_0(clk_0),                              
.clk_90(clk_90),                            
.idelay_ctrl_rdy(idelay_ctrl_rdy),     
.clk_200(clk_200),                   
               
.sys_rst(sys_rst),
.sys_rst90(sys_rst90),
.test_bus(test_bus)
); 


             
 mem_clk_rst mem_clk_rst(	
.SYS_CLK_P	(SYS_CLK_P),
.SYS_CLK_N	(SYS_CLK_N),
.CLK200_P	(CLK200_P),
.CLK200_N	(CLK200_N),
.SYS_RESET_IN	(SYS_RESET_IN),	   
                  
                   .CLK               (clk_0),                              
                   .CLK90             (clk_90),                            
                   .CLK200            (clk_200),                                              
                   .sys_rst           (sys_rst),
                   .sys_rst90         (sys_rst90),
                   .sys_rst200        (sys_rst200),
		   .DDR2_CK	(cntrl0_DDR2_CK),
                   .DDR2_CK_N	(cntrl0_DDR2_CK_N)
                 );   
                                    
                                    
        mem_io_ctrl mem_io_ctrl(     
                                .CLK200     (clk_200),
	                          .RESET      (sys_rst200),
	                          .RDY_STATUS (idelay_ctrl_rdy) 
                               );



   
mem_test mem_test
                (
                   .CLK(clk_0),
                   .RESET(sys_rst),
		   .phy_init_initialization_done(phy_init_initialization_done),
                   .WDF_ALMOST_FULL(wr_df_almost_full),
                   .AF_ALMOST_FULL (af_almost_full),
                   .BURST_LENGTH(burst_length),
                   .READ_DATA_VALID(rd_data_valid),
                   .READ_DATA_FIFO_OUT(rd_data_fifo_out),
                   .APP_AF_ADDR(app_af_addr),
                   .APP_AF_WREN(app_af_wren),
                   .APP_WDF_DATA(app_wr_df_data),
                   .APP_MASK_DATA(app_mask_df_data),
                   .APP_WDF_WREN(app_wr_df_wren),
                   .ERROR(cntrl0_ERROR)
                  );
                                          

       //-----------------------------------------------------------------

       //  ILA/ICON Core wire declarations

       //-----------------------------------------------------------------

         wire [35:0]  control_chipscope;

         wire [100:0] data_chipscope;

         wire [4:0]   trig_chipscope;

         

       //-----------------------------------------------------------------

       //  ILA core instance

       //-----------------------------------------------------------------

         ila i_ila

           (

             .control(control_chipscope),

             .clk(clk_0),     // Global Clock to all modules (CLK0 DCM)

             .data(data_chipscope),

             .trig0(trig_chipscope)   

           );

       

       //-----------------------------------------------------------------

       //  ICON core instance

       //-----------------------------------------------------------------

         icon i_icon

           (

             .control0(control_chipscope)

           );

           

       assign trig_chipscope = { 2'd0, test_we_n, test_cas_n, test_ras_n}; // width = 5 bits

       assign data_chipscope = { 5'd0, rd_data_valid, test_bus[43:0], rise_data_clk0_test[23:0], fall_data_clk0_test[23:0], test_we_n, test_cas_n, test_ras_n};

 

//end of put in main code

 

 endmodule
 

//-------------------------------------------------------------------

//  ILA core module declaration

//-------------------------------------------------------------------

 

module ila

  (

    control,

    clk,
             data,

    trig0

  );

  input [35:0] control;

  input clk;

  input [100:0] data;

  input [4:0] trig0;

endmodule

 

 

 

//-------------------------------------------------------------------

//  ICON core module declaration

//-------------------------------------------------------------------

module icon 

  (

      control0

  );

  output [35:0] control0;

  

endmodule