mem_test_rom_addr.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

module mem_test_rom_addr (
input         clk0,
input         rst,
input         bkend_wraddr_en,

output reg [35:0]  app_af_addr,
output reg      app_af_WrEn

                );
                    


wire [8:0]     wr_rd_addr;
wire           wr_rd_addr_en;

reg [5:0]     wr_addr_count;
reg           bkend_wraddr_en_reg; 
reg           wr_rd_addr_en_reg;
reg           bkend_wraddr_en_3r;

wire [31:0]    unused_data_in;
wire [3:0]     unused_data_in_p;
wire           gnd;
wire [31:0]    addr_out;

assign unused_data_in = 32'h00000000;
assign unused_data_in_p = 4'h0;
assign gnd = 1'b0;

//ADDRESS generation for Write and Read Address FIFOs

//ROM with address patterns
//512x36 mode is used with addresses 0-127 for storing write addresses and 
//addresses (128-511) for storing read addresses

//read 11
// write 10

  defparam
	  wr_rd_addr_lookup.INIT_00 = 256'h0103C154_0103C198_0103C088_0103C0EC_00023154_00023198_00023088_000230EC,
	  wr_rd_addr_lookup.INIT_01 = 256'h10023154_10023198_10023088_100230EC_1103C154_1103C198_1103C088_1103C0EC,
	  wr_rd_addr_lookup.INIT_02 = 256'h0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC, 
	  wr_rd_addr_lookup.INIT_03 = 256'h1083C154_1083C198_1083C088_1083C0EC_10823154_10823198_10823088_108230EC,
	  wr_rd_addr_lookup.INIT_04 = 256'h0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC,
	  wr_rd_addr_lookup.INIT_05 = 256'h1043C154_1043C198_1043C088_1043C0EC_10423154_10423198_10423088_104230EC,
	  wr_rd_addr_lookup.INIT_06 = 256'h00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC,
	  wr_rd_addr_lookup.INIT_07 = 256'h10C3C154_10C3C198_10C3C088_10C3C0EC_10C23154_10C23198_10C23088_10C230EC;

   

  
RAMB16_S36 wr_rd_addr_lookup (
                                .DO(addr_out[31:0]), 
                                .DOP(), 
                                .ADDR(wr_rd_addr[8:0]), 
                                .CLK(clk0), 
                                .DI(unused_data_in[31:0]), 
                                .DIP(unused_data_in_p[3:0]), 
                                .EN(wr_rd_addr_en_reg), 
                                .SSR(gnd),
                                .WE(gnd)
                                );

                         
assign wr_rd_addr_en = (bkend_wraddr_en == 1'b1);

always @ (posedge clk0) begin
  if (rst) begin
     wr_rd_addr_en_reg <= 1'b0;
  end else begin
     wr_rd_addr_en_reg <= wr_rd_addr_en;
  end 
end

//register backend enables 
always @ (posedge clk0) begin
  if (rst) begin
     bkend_wraddr_en_reg <= 1'b0; 
     bkend_wraddr_en_3r  <= 1'b0; 
   end else begin
     bkend_wraddr_en_reg <= bkend_wraddr_en;  
     bkend_wraddr_en_3r  <= bkend_wraddr_en_reg;
   end
end

// Fifo enables
always @ (posedge clk0) begin
  if (rst) begin
     app_af_WrEn <= 1'b0;
  end else begin
     app_af_WrEn <= bkend_wraddr_en_3r;

  end
end
  
// FIFO addresses                           
always @ (posedge clk0) begin
  if (rst) begin
     app_af_addr <= 36'h00000;
     
  end else if (bkend_wraddr_en_3r) begin // THIS NEEDS TO BE CHANGED. should be [31:28],4'h0,[27:0]
     app_af_addr <= {addr_out[31:28], 4'h0,addr_out[27:0]};
     
  end else begin
     app_af_addr <= 36'h00000;
    
  end
end      

// address input for ROM
always @ (posedge clk0) begin
  if (rst) begin
      wr_addr_count[5:0] <= 6'b111111;
  end else if (bkend_wraddr_en) begin
      wr_addr_count[5:0] <= wr_addr_count[5:0] + 1;
  end else begin
      wr_addr_count[5:0] <= wr_addr_count[5:0];
  end
end                    


assign wr_rd_addr[8:0] = (bkend_wraddr_en_reg) ? {3'b000,wr_addr_count[5:0]} :
                         9'b000000000;

endmodule