mem_phy_ctl_io.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////


module mem_phy_ctl_io (
input                    clk,
input                    rst,
input[`row_address-1:0]   ctrl_address,
input[`bank_address-1:0]    ctrl_ba,
input         ctrl_ras_n,
input         ctrl_cas_n,
input         ctrl_we_n,
input [`cs_width-1:0]        ctrl_cs_n,
input   [`odt_width-1:0]       ctrl_odt, 
input [`row_address-1:0] 	phy_init_address,   
input [`bank_address-1:0] 	phy_init_ba,   
input 			phy_init_ras_n,   
input 			phy_init_cas_n,   
input 			phy_init_we_n,   
input [`cs_width-1:0] 	phy_init_cs_n, 
input [`cke_width-1:0] 	phy_init_cke, 
input                         phy_init_initialization_done,

output [`row_address-1:0] DDR_ADDRESS,
output [`bank_address-1:0]  DDR_BA,     
output        DDR_RAS_L, 
output        DDR_CAS_L,  
output        DDR_WE_L,
output reg    test_ras_n,
output reg    test_cas_n,
output reg    test_we_n,
output   [`cke_width-1:0]      DDR_CKE,
output   [`odt_width-1:0]      DDR_ODT,    
output  [`cs_width-1:0]      DDR_CS_L

                   );
                   

   reg 			     ras_n_r;   
   reg 			     cas_n_r;   
   reg 			     we_n_r;
   reg [`cs_width-1:0] 	     cs_n_r;   
   reg [`row_address-1:0]    address_r;   
   reg [`bank_address-1:0]   ba_r;
  // synthesis attribute iob of ras_n_r is true; 
  // synthesis attribute iob of cas_n_r is true; 
  // synthesis attribute iob of we_n_r is true; 
  // synthesis attribute iob of cs_n_r is true; 
  // synthesis attribute iob of address_r is true; 
  // synthesis attribute iob of ba_r is true;     

always@(posedge clk)begin
   if(rst)begin
     ras_n_r <= 1'd1;
     cas_n_r <= 1'd1;
     we_n_r  <= 1'd1;
     cs_n_r  <= `cs_width'd0;
     address_r <= `row_address'd0;
     ba_r <= `bank_address'd0;
     test_ras_n <= 1'd1;
     test_cas_n <= 1'd1;
     test_we_n  <= 1'd1;
   end
   else begin
     if(phy_init_initialization_done)begin
	ras_n_r <= ctrl_ras_n;
	cas_n_r <= ctrl_cas_n;
	we_n_r  <= ctrl_we_n;
	cs_n_r <= ctrl_cs_n;
	address_r <= ctrl_address;
	ba_r <= ctrl_ba;
	test_ras_n <= ctrl_ras_n;
	test_cas_n <= ctrl_cas_n;
	test_we_n  <= ctrl_we_n;
     end else begin
	ras_n_r <= phy_init_ras_n;
	cas_n_r <= phy_init_cas_n;
	we_n_r  <= phy_init_we_n;
	cs_n_r <= phy_init_cs_n;
	address_r <= phy_init_address;
	ba_r <= phy_init_ba;
     end // else: !if(phy_init_initialization_done)
   end // else: !if(rst)
end // always@ (posedge clk)
   
	
 
      
      
   


OBUF r0(
        .I(ras_n_r),
        .O(DDR_RAS_L)
       );

OBUF r1(
        .I(cas_n_r),
        .O(DDR_CAS_L)
       );

OBUF r2(
        .I(we_n_r),
        .O(DDR_WE_L)
       );


OBUF OBUF_cs0
	(
        .I(cs_n_r[0]),
        .O(DDR_CS_L[0])
      );


OBUF OBUF_cs1
        (
	        .I(cs_n_r[1]),
		        .O(DDR_CS_L[1])
			      );



OBUF OBUF_cke0
	(
        .I(phy_init_cke[0]),
        .O(DDR_CKE[0])
      );

OBUF OBUF_cke1
	(
        .I(phy_init_cke[1]),
        .O(DDR_CKE[1])
      );


OBUF OBUF_odt0
      (
	  .I(ctrl_odt[0]),
        .O(DDR_ODT[0])
      );


       
OBUF OBUF_r0
	(
        .I(address_r[0]),
        .O(DDR_ADDRESS[0])
      );

OBUF OBUF_r1
	(
        .I(address_r[1]),
        .O(DDR_ADDRESS[1])
      );

OBUF OBUF_r2
	(
        .I(address_r[2]),
        .O(DDR_ADDRESS[2])
      );

OBUF OBUF_r3
	(
        .I(address_r[3]),
        .O(DDR_ADDRESS[3])
      );

OBUF OBUF_r4
	(
        .I(address_r[4]),
        .O(DDR_ADDRESS[4])
      );

OBUF OBUF_r5
	(
        .I(address_r[5]),
        .O(DDR_ADDRESS[5])
      );

OBUF OBUF_r6
	(
        .I(address_r[6]),
        .O(DDR_ADDRESS[6])
      );

OBUF OBUF_r7
	(
        .I(address_r[7]),
        .O(DDR_ADDRESS[7])
      );

OBUF OBUF_r8
	(
        .I(address_r[8]),
        .O(DDR_ADDRESS[8])
      );

OBUF OBUF_r9
	(
        .I(address_r[9]),
        .O(DDR_ADDRESS[9])
      );

OBUF OBUF_r10
	(
        .I(address_r[10]),
        .O(DDR_ADDRESS[10])
      );

OBUF OBUF_r11
	(
        .I(address_r[11]),
        .O(DDR_ADDRESS[11])
      );

OBUF OBUF_r12
	(
        .I(address_r[12]),
        .O(DDR_ADDRESS[12])
      );

OBUF OBUF_r13
	(
        .I(address_r[13]),
        .O(DDR_ADDRESS[13])
      );


OBUF OBUF_b0
	(
        .I(ba_r[0]),
        .O(DDR_BA[0])
      );

OBUF OBUF_b1
	(
        .I(ba_r[1]),
        .O(DDR_BA[1])
      );

      


            
endmodule