mem_phy_calib.v

xilinx公司的ＤＤＲ实现源码

	 dq_dec_count_r <= 2'd0;
	 dq_count_r <= 3'd1; // starts with a default of 1 because the first dq is calibrated in the dqs calibration 
	 phy_calib_dq_dlyinc <= `data_width'd0;
	 phy_calib_dq_dlyce <= `data_width'd0;
	 phy_calib_dq_dlyrst <= `data_width'hffffffffffffffff;

      end // if (reset90 || ~idelay_ctrl_rdy)
      else begin

	 phy_calib_dq_dlyrst <= `data_width'd0;

	 
        case(dq_state_r)
	
	DQ_IDLE: begin
	             
		    phy_calib_dq_dlyinc[(dqs_count_r*8) + 0] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 0] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 1] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 1] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 2] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 2] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 3] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 3] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 4] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 4] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 5] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 5] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 6] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 6] <= add_dq_delay_r;
	   	    phy_calib_dq_dlyinc[(dqs_count_r*8) + 7] <= add_dq_delay_r;
	            phy_calib_dq_dlyce[(dqs_count_r*8) + 7] <= add_dq_delay_r;
                    if(dq_calib_begin_r) dq_state_r <= DQ_DQ_CHECK;
	         end 

        DQ_DQ_CHECK: begin
	   if((capture_data_r[(dqs_count_r*8) + dq_count_r] == capture_data_r[((dqs_count_r*8) + `data_width)+dq_count_r] ))begin
	        if(dq_dec_count_r > 2'd0) // if no data match to start with increment to find the window. If there was a decrement and
		  dq_state_r <= DQ_DQ_SELECT; // data does not match now then the end of the window has been foune. 
	        else
		  dq_state_r <= DQ_DQ_INC;      
	   end else begin
	      if((dq_inc_count_r == 2'd0)) // if there is a data match to start with decrement the window. If there was an increment 
		                             // and then a data match (dq_inc_counter_r will be > 0 in case of previous increment). the 
                  dq_state_r <= DQ_DQ_DEC;   // window for the DQ has been found. 
                else    
	          dq_state_r <= DQ_DQ_SELECT;
	   end // else: !if((capture_data_r[(dqs_count_r*8) + dq_count_r] == capture_data_r[((dqs_count_r*8) + `data_width)+dq_count_r] ))
	end // case: DQ_DQ_CHECK

	DQ_DQ_DEC: begin
	   //phy_calib_dq_dlyce[(dqs_count_r*8) + dq_count_r] <= 1'd1;
	   dq_state_r <= DQ_DQ_WAIT0;
	   dq_dec_count_r <= dq_dec_count_r + 1'd1;
	end

	DQ_DQ_INC: begin
	   // phy_calib_dq_dlyce[(dqs_count_r*8) + dq_count_r] <= 1'd1;
	  //  phy_calib_dq_dlyinc[(dqs_count_r*8) + dq_count_r] <= 1'd1;
	   dq_state_r <= DQ_DQ_WAIT0;
	   dq_inc_count_r <= dq_inc_count_r + 1'd1;
	end
	  

	  DQ_DQ_WAIT1: dq_state_r <= DQ_DQ_WAIT2;

	  DQ_DQ_WAIT0: begin
                 dq_state_r <= DQ_DQ_WAIT1;
	        // phy_calib_dq_dlyinc[(dqs_count_r*8) + dq_count_r] <= 1'd0;
	       //  phy_calib_dq_dlyce[(dqs_count_r*8) + dq_count_r] <= 1'd0;
	     end

	  DQ_DQ_WAIT2: begin
	     if(&dq_dec_count_r || &dq_inc_count_r)
	       dq_state_r <= DQ_DQ_SELECT;
	     else
	       dq_state_r <= DQ_DQ_CHECK;
	  end


	  DQ_DQ_SELECT: begin
	     if(&dq_count_r) begin // if all the dq bits are calibrated 
		dq_state_r <= DQ_DQ_CALIB_DONE0;
		dq_count_r <= 3'd1;
		dq_calib_done_r <= 1'd1;
		dq_dec_count_r <= 2'd0;
		dq_inc_count_r <= 2'd0;
	     end else begin
		dq_state_r <= DQ_DQ_CHECK;
		dq_count_r <= dq_count_r + 1'd1;
	     end
	  end // case: DQ_DQ_SELECT

	  DQ_DQ_CALIB_DONE0: begin
	     dq_state_r <= DQ_DQ_CALIB_DONE1;
	     dq_calib_done_r <= 1'd1;
	  end
	  
	 DQ_DQ_CALIB_DONE1: begin
	     dq_state_r <= DQ_IDLE;
	     dq_calib_done_r <= 1'd0;
	  end
	endcase // case(dq_state_r)
	 

      end // else: !if(reset90 || ~idelay_ctrl_rdy)
   end // always@ (posedge clk90)
   
	     
		
		


/*
// reg read enable to take care of additive latency, ecc and registerd values stages  
  generate
   genvar rd_i;
     for (rd_i = 0; rd_i<4; rd_i=rd_i+1)
       begin: dqs_en
	   always@(posedge clk90)begin
	      if(reset90)
                rd_en_stages_r <= 5'd0;
            else begin 
                 rd_en_stages_r[0] <= ctrl_rden | phy_init_rden;
                 rd_en_stages_r[rd_i + 1] <= rd_en_stages_r[rd_i];
            end
           end
end
endgenerate
*/

/*
// stages for selecting the final read enable 
  generate
   genvar re_i;
     for (re_i = 0; re_i<4; re_i=re_i+1)
       begin: rd_en
	   always@(posedge clk90)begin
	      if(reset90)
	      begin
                read_en_r[4:1] <= 4'd0;
                rd_en_stages_r[4:1] <= 4'd0;
		end
            else begin 
                 read_en_r[re_i + 1] <= read_en_r[re_i];
                 rd_en_stages_r[re_i +1] <= rd_en_stages_r[re_i];
            end
           end
end
endgenerate
*/

          always@(negedge clk90) begin
	     if(reset90) begin
		ctrl_rden_270_r <= 1'd0;
		phy_init_rden_270_r <= 1'd0;
	     end else begin
		ctrl_rden_270_r <= ctrl_rden;
		phy_init_rden_270_r <= phy_init_rden;
             end
          end
		

	   always@(posedge clk90)begin
	      if(reset90)
	      begin
                read_en_r <= 5'd0;
                rd_en_stages_r <= 8'd0;
		end
            else begin 
                 read_en_r[0] <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
		 read_en_r[1] <= read_en_r[0];
		 read_en_r[2] <= read_en_r[1];
	         read_en_r[3] <= read_en_r[2];
		 read_en_r[4] <= read_en_r[3];
                 rd_en_stages_r[0] <= ctrl_rden_270_r | phy_init_rden_270_r;
		 rd_en_stages_r[1] <= rd_en_stages_r[0];
		 rd_en_stages_r[2] <= rd_en_stages_r[1];
		 rd_en_stages_r[3] <= rd_en_stages_r[2];
		 rd_en_stages_r[4] <= rd_en_stages_r[3];
	         rd_en_stages_r[5] <= rd_en_stages_r[4];
	         rd_en_stages_r[6] <= rd_en_stages_r[5];
	         rd_en_stages_r[7] <= rd_en_stages_r[6];
					  
            end
	   end   
   

   //readen calibration

   always@(posedge clk90) begin
      if(reset90) begin
	 stg2_read_r2 <= 1'd0;
	 stg2_read_r3 <= 1'd0;
	 stg1_read_r2 <= 1'd0;
      end
      else begin
	 stg2_read_r2 <= stg2_read_r1;
 	 stg2_read_r3 <= stg2_read_r2;
	 stg1_read_r2 <= stg1_read_r1;
      end
   end // always@ (posedge clk90)

      always@(negedge clk90) begin
      if(reset90) begin
	 stg2_read_r1 <= 1'd0;
	 stg1_read_r1 <= 1'd0;
      end
      else begin
	 stg2_read_r1 <= phy_init_st2_read;
	 stg1_read_r1 <= phy_init_st1_read;
      end
   end // always@ (posedge clk90)
   

   assign read_en_r1_edge = read_en_r[0] & ~read_en_r[1];
   assign read_en_r2_edge = read_en_r[1] & ~read_en_r[2];
   assign read_en_r3_edge = read_en_r[2] & ~read_en_r[3];
   assign read_en_r4_edge = read_en_r[3] & ~read_en_r[4];


always @(posedge clk90) begin
   if(reset90)
     data_match <= 1'b0;
   else 
     data_match <= ( (capture_data_r[(rden_count_r*8)] == 1) &&
			 (capture_data_r[(rden_count_r*8+1)] == 0)&&
			  (capture_data_r[(rden_count_r*8+2)] == 1)&&
			  (capture_data_r[(rden_count_r*8+3)] == 0)&&
                          (capture_data_r[(rden_count_r*8)+`data_width ] == 1) &&
			 (capture_data_r[(rden_count_r*8+1)+ `data_width] == 0)&&
			  (capture_data_r[(rden_count_r*8+2)+ `data_width] == 1)&&
			 (capture_data_r[(rden_count_r*8+3)+ `data_width] == 0));
end // always @ (posedge clk90)
   
			   
   
   	 
 
   always@(posedge clk90) begin
      if(reset90)begin
	 read_en_stg_r <= 2*`data_strobe_width'd0;
	 second_calib_done_90_r <= 1'd0;
         rden_count_r <= `data_strobe_width'd0;
      end
      else begin
	
         if(rden_count_r ==  (`data_strobe_width))
            second_calib_done_90_r <= 1'd1;
          
        case({data_match, read_en_r1_edge, read_en_r2_edge, read_en_r3_edge, read_en_r4_edge})
	   5'b11000: begin
              read_en_stg_r[((rden_count_r*2) + 1)] <= 1'b0;
	      read_en_stg_r[(rden_count_r*2)] <= 1'b0;
	     // second_calib_done <= 1'd1;
              rden_count_r <= rden_count_r + 1'd1;
	   end
	   5'b10100: begin
            //   read_en_stg_r [(rden_count_r*2'd2)+1 :rden_count_r*2)] <= 2'b01;
              read_en_stg_r[((rden_count_r*2) + 1)] <= 1'b0;
	      read_en_stg_r[(rden_count_r*2)] <= 1'b1;
	     //  second_calib_done <= 1'd1;
               rden_count_r <= rden_count_r + 1'd1;
	   end
	   5'b10010: begin 
              //  read_en_stg_r [(rden_count_r*2)+1 :rden_count_r*2)] <= 2'b10;
              read_en_stg_r[((rden_count_r*2) + 1)] <= 1'b1;
	      read_en_stg_r[(rden_count_r*2)] <= 1'b0;
	      //  second_calib_done <= 1'd1;
                rden_count_r <= rden_count_r + 1'd1;
	   end
	   5'b10001: begin
             //  read_en_stg_r[(rden_count_r*2)+1 :rden_count_r*2)]  <= 2'b11;
              read_en_stg_r[((rden_count_r*2) + 1)] <= 1'b1;
	      read_en_stg_r[(rden_count_r*2)] <= 1'b1;
	      // second_calib_done <= 1'd1;
               rden_count_r <= rden_count_r + 1'd1;
	   end
	endcase // case({data_match, read_en_r1_edge, read_en_r2_edge, read_en_r3_edge, read_en_r4_edge})
      end // else: !if(reset90)
   end // always@ (posedge clk90)
   
   always@(posedge clk0) begin
      if(reset0)begin
         first_calib_done <= 1'd0;
	 second_calib_done <= 1'd0;
	 state_r_test      <= 4'd0;
	 capture_data_r2_test <= `data_width*2'd0;
	 dqs_count_r1_test   <= `data_strobe_width'd0; 
      end else begin
	 first_calib_done <= first_calib_done_90_r;
	 second_calib_done <= second_calib_done_90_r;
	 state_r_test      <= state_r;
	 capture_data_r2_test <= capture_data_r2;
	 dqs_count_r1_test <= dqs_count_r1;
      end
   end
   
	   
    always@(posedge clk90) begin
      if(reset90)begin
	 phy_calib_rden <= `data_strobe_width'd0;
      end
      else begin
	 case({stg2_read_r2,read_en_stg_r[1:0]})
	   3'b000: phy_calib_rden[0]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[0]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[0]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[0]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[1:0]})

	 case({stg2_read_r2,read_en_stg_r[3:2]})
	   3'b000: phy_calib_rden[1]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[1]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[1]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[1]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[3:2]})

	 case({stg2_read_r2,read_en_stg_r[5:4]})
	   3'b000: phy_calib_rden[2]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[2]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[2]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[2]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[5:4]})

	 case({stg2_read_r2,read_en_stg_r[7:6]})
	   3'b000: phy_calib_rden[3]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[3]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[3]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[3]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[7:6]})


	 case({stg2_read_r2,read_en_stg_r[9:8]})
	   3'b000: phy_calib_rden[4]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[4]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[4]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[4]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[1:0]})

	 case({stg2_read_r2,read_en_stg_r[11:10]})
	   3'b000: phy_calib_rden[5]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[5]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[5]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[5]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[3:2]})

	 case({stg2_read_r2,read_en_stg_r[13:12]})
	   3'b000: phy_calib_rden[6]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[6]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[6]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[6]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[5:4]})

	 case({stg2_read_r2,read_en_stg_r[15:14]})
	   3'b000: phy_calib_rden[7]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+3];
	   3'b001: phy_calib_rden[7]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+4];
	   3'b010: phy_calib_rden[7]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+5];
	   3'b011: phy_calib_rden[7]  <= rd_en_stages_r[ADDITIVE_LATENCY_VALUE + ECC_VALUE + REGISTERED_VALUE+6];
	 endcase // case({stg2_read_r2,read_en_stg_r[7:6]})

      end // else: !if(reset90)
    end // always@ (posedge clk90)
   
  

endmodule // phy_calib