mem_phy_init.v

xilinx公司的ＤＤＲ实现源码

       cas_check_count_r <= cas_check_count_r - 1'b1;
end

always @ (posedge clk0) begin
   if (rst) 
      rdburst_cnt_r <= 3'd0;
   else if ((cas_check_count_r == 4'b0010))
      rdburst_cnt_r <= burst_cnt;      
   else if (rdburst_cnt_r > 3'd0)                  
      rdburst_cnt_r <= rdburst_cnt_r - 1'b1;
end // always @ (posedge clk0)


//read enable to data path
always @ (*) begin
   if ((rdburst_cnt_r == 3'd0)) begin
      ctrl_read_en <= 1'b0;
   end else begin
      ctrl_read_en <= 1'b1;
   end
end


always@(posedge clk0)
begin
   if(rst) 
     wdf_rden_r <= 1'd0;
   else if ((init_state_r == INIT_FIRST_WRITE) || (init_state_r == INIT_PATTERN_WRITE))
      wdf_rden_r <= 1'd1;
   else
     wdf_rden_r <= 1'd0;
end
   
   
   
always@(posedge clk0)
begin
   if(rst) begin
      wdf_rden_r1 <= 1'd0;
      wdf_rden_r2 <= 1'd0;
      wdf_rden_r3 <= 1'd0;
      wdf_rden_r4 <= 1'd0;
      wdf_rden_r5 <= 1'd0;
      wdf_rden_r6 <= 1'd0;
      wdf_rden_r7 <= 1'd0;
      wdf_rden_r8 <= 1'd0;
      wdf_rden_r9 <= 1'd0;
   end
   else begin
      wdf_rden_r1 <= wdf_rden_r;
      wdf_rden_r2 <= wdf_rden_r1;
      wdf_rden_r3 <= wdf_rden_r2;
      wdf_rden_r4 <= wdf_rden_r3;
      wdf_rden_r5 <= wdf_rden_r4;
      wdf_rden_r6 <= wdf_rden_r5;
      wdf_rden_r7 <= wdf_rden_r6;
      wdf_rden_r8 <= wdf_rden_r7;
      wdf_rden_r9 <= wdf_rden_r8;
   end // else: !if(rst)
end // always@ (posedge clk0)

   
always@(posedge clk0)
begin
   if(rst) begin
      phy_init_wdf_rden<= 1'd0;
   end else begin
       case(ADDITIVE_LATENCY_VALUE  + CAS_LATENCY_VALUE + REGISTERED_VALUE)
	 4'b0011:phy_init_wdf_rden<= wdf_rden_r | wdf_rden_r1 | wdf_rden_r2 | wdf_rden_r3;
	 4'b0100:phy_init_wdf_rden<= wdf_rden_r1 | wdf_rden_r2 | wdf_rden_r3 | wdf_rden_r4;
         4'b0101:phy_init_wdf_rden<= wdf_rden_r2 | wdf_rden_r3 | wdf_rden_r4 | wdf_rden_r5;
	 4'b0110:phy_init_wdf_rden<= wdf_rden_r3 | wdf_rden_r4 | wdf_rden_r5 | wdf_rden_r6;
	 4'b0111:phy_init_wdf_rden<= wdf_rden_r4 | wdf_rden_r5 | wdf_rden_r6 | wdf_rden_r7;
	 4'b1000:phy_init_wdf_rden<= wdf_rden_r5 | wdf_rden_r6 | wdf_rden_r7 | wdf_rden_r8;
	 4'b1001:phy_init_wdf_rden<= wdf_rden_r6 | wdf_rden_r7 | wdf_rden_r8 | wdf_rden_r9;
       endcase // case(ADDITIVE_LATENCY_VALUE  + CAS_LATENCY_VALUE + REGISTERED_VALUE)
   end // else: !if(rst)
end // always@ (posedge clk0)
   
    


assign phy_init_rden  = ctrl_read_en;



always @ (posedge clk0) begin
  if (rst || init_memory_r)
     initalization_done_r <= 1'd0;
  else if((second_calib_done) && ((init_state_r == INIT_PRECHARGE_WAIT) && (rfc_count_r == 6'd0)))
       initalization_done_r <= 1'd1;
end

always @ (posedge clk0) begin
  if (rst) begin
     init_state_r <= INIT_IDLE;
     init_state_r1 <= INIT_IDLE;
     init_state_r2 <= INIT_IDLE;
 end else begin
     init_state_r <= init_next_state;
     init_state_r1 <= init_state_r;
     init_state_r2 <= init_state_r1;
     end
end
   
 	
// init state machine
always @ (*)
 begin
	 
    init_next_state = init_state_r;
    
   case (init_state_r)
     INIT_IDLE : begin
        if (init_memory_r && done_200us_r == 1'b1) begin
           case (init_count_r ) // synthesis parallel_case full_case
             4'h0 : init_next_state = INIT_COUNT_200;            
             4'h1 : if (count_200cycle_done_r) init_next_state = INIT_PRECHARGE;
             4'h2 : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE; //emr(2)
             4'h3 : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE; //emr(3);
             4'h4 : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE; //emr;       
             4'h5 : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE; //lmr;   
             4'h6 : if (rfc_count_r == 6'b00000) init_next_state = INIT_PRECHARGE;    
             4'h7 : if (rfc_count_r == 6'b00000) init_next_state = INIT_AUTO_REFRESH; 
             4'h8 : if (rfc_count_r == 6'b00000) init_next_state = INIT_AUTO_REFRESH;
             4'h9 : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE;
             4'hA : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE;
             4'hB : if (rfc_count_r == 6'b00000) init_next_state = INIT_LOAD_MODE;
             4'hC : if (rfc_count_r == 6'b00000) init_next_state = INIT_COUNT_200;
	     4'hD :  begin  
             	if( (chip_cnt_r < `cs_width-1))
                  init_next_state = INIT_DEEP_MEMORY_ST;
		else  if (count_200cycle_done_r)  
                  init_next_state = INIT_DUMMY_ACTIVE; //  init_next_state = INIT_DUMMY_READ_CYCLES;
		else
		  init_next_state = INIT_IDLE;
	     end
             4'hE :if (second_calib_done) init_next_state = INIT_PRECHARGE;
             4'hF :  begin    
                if (second_calib_done) 
                   init_next_state = INIT_IDLE;
                end
	     
	     default: init_next_state = INIT_IDLE;
	     
           endcase // case(init_count)                  

        end 
     end // case: IDLE
      INIT_DEEP_MEMORY_ST : init_next_state = INIT_IDLE;     
      INIT_COUNT_200 : init_next_state = INIT_COUNT_200_WAIT; 
      INIT_COUNT_200_WAIT : if (count_200cycle_done_r) init_next_state = INIT_IDLE;
      INIT_DUMMY_ACTIVE       : init_next_state = INIT_DUMMY_ACTIVE_WAIT;
      INIT_DUMMY_ACTIVE_WAIT  : if (rfc_count_r == 6'd0) init_next_state = INIT_FIRST_WRITE;
      INIT_FIRST_READ_WAIT : begin
        if((first_calib_done)) begin
	   if(rfc_count_r == 6'd0)
               init_next_state = INIT_PATTERN_WRITE ;
       end else 
         init_next_state = INIT_FIRST_READ;
       end
     INIT_FIRST_WRITE:  init_next_state = INIT_FIRST_WRITE_READ;
     INIT_FIRST_WRITE_READ         : if (rfc_count_r == 6'd0) init_next_state = INIT_FIRST_READ;
     INIT_FIRST_READ : init_next_state = INIT_FIRST_READ_WAIT;
     INIT_PRECHARGE          : init_next_state = INIT_PRECHARGE_WAIT;
     INIT_PRECHARGE_WAIT     : if (rfc_count_r == 6'd0) init_next_state = INIT_IDLE;                
     INIT_LOAD_MODE      : init_next_state = INIT_MODE_REGISTER_WAIT;
     INIT_MODE_REGISTER_WAIT : if (rfc_count_r == 6'd0) init_next_state = INIT_IDLE;            
     INIT_AUTO_REFRESH       : init_next_state = INIT_AUTO_REFRESH_WAIT;
     INIT_AUTO_REFRESH_WAIT  :if (rfc_count_r == 6'd0) init_next_state = INIT_IDLE;                 
     INIT_ACTIVE             : init_next_state = INIT_ACTIVE_WAIT;
     INIT_ACTIVE_WAIT        : if (rfc_count_r == 6'd0) init_next_state = INIT_IDLE;
     INIT_PATTERN_WRITE        : init_next_state = INIT_PATTERN_WRITE_READ;
     INIT_PATTERN_WRITE_READ    :if (rfc_count_r == 6'd0) init_next_state = INIT_PATTERN_READ;
     INIT_PATTERN_READ : init_next_state = INIT_PATTERN_READ_WAIT;
     INIT_PATTERN_READ_WAIT : begin
        if((second_calib_done))begin
	   if (rfc_count_r == 6'd0)
              init_next_state = INIT_PRECHARGE;
       end  else if (rfc_count_r == 6'd0)
         init_next_state = INIT_PATTERN_READ;
       end
     
                            
   endcase // case(state)
end // always @ (...


// commands to the memory
always @ (posedge clk0) begin
   if (rst)
      ddr2_ras_r <= 1'b1;
 //  else if (init_state_r == INIT_LOAD_MODE || init_state_r == INIT_PRECHARGE || init_state_r == INIT_ACTIVE 
//                || init_state_r == INIT_AUTO_REFRESH || init_state_r == INIT_DUMMY_ACTIVE )
   else if (init_state_r < INIT_FIRST_WRITE)
      ddr2_ras_r <= 1'b0;
 else ddr2_ras_r <= 1'b1;
end

// commands to the memory
always @ (posedge clk0) begin
   if (rst) 
      ddr2_cas_r <= 1'b1;
  // else if (init_state_r == INIT_LOAD_MODE || init_state_r == INIT_AUTO_REFRESH 
 //               || init_state_r == INIT_FIRST_WRITE || init_state_r == INIT_FIRST_READ || 
  //              init_state_r== INIT_PATTERN_READ || init_state_r == INIT_PATTERN_WRITE )
    else if ((init_state_r > INIT_PRECHARGE) && (init_state_r < INIT_COUNT_200))
      ddr2_cas_r <= 1'b0;
   else
      ddr2_cas_r <= 1'b1;
end // always @ (posedge clk0)

// commands to the memory
always @ (posedge clk0) begin
   if (rst) 
      ddr2_we_r <= 1'b1;
   else if (init_state_r == INIT_PATTERN_WRITE || init_state_r == INIT_FIRST_WRITE
                || init_state_r == INIT_LOAD_MODE || init_state_r == INIT_PRECHARGE) 
      ddr2_we_r <= 1'b0;
   else ddr2_we_r <= 1'b1;
end

//register commands to the memory
always @ (posedge clk0) begin
   if (rst) begin
      ddr2_ras_r1 <= 1'b1;
      ddr2_cas_r1 <= 1'b1;
      ddr2_we_r1 <= 1'b1;
   end else begin
      ddr2_ras_r1  <= ddr2_ras_r; 
      ddr2_cas_r1  <= ddr2_cas_r;
      ddr2_we_r1   <= ddr2_we_r;
  end
end

   
// address during init 
always @ (posedge clk0) begin
   if (rst) 
       ddr2_address_init_r <= `row_address'h0000;
   else begin
      if (init_state_r1 == INIT_PRECHARGE) begin
         ddr2_address_init_r <= `row_address'h0400; 						//A10 = 1 for precharge all		   
      end else if ( init_state_r1 == INIT_LOAD_MODE && init_count_r == 4'h5) begin 
	 ddr2_address_init_r <= ext_mode_reg; 						// A0 == 0 for DLL enable  
      end else if ( init_state_r1 == INIT_LOAD_MODE && init_count_r == 4'h6) begin
         ddr2_address_init_r <= (`row_address'h0100 | load_mode_reg); 			// A8 == 1 for DLL reset
      end else if (init_state_r1 == INIT_LOAD_MODE && init_count_r ==4'hA) begin
         ddr2_address_init_r <= load_mode_reg;  				// Write recovery = 4; cas_latency = 4; burst length = 4
      end else if (init_state_r1 == INIT_LOAD_MODE && init_count_r ==4'hB) begin
         ddr2_address_init_r <= (`row_address'h0380 | ext_mode_reg); // OCD DEFAULT
      end else if (init_state_r1 == INIT_LOAD_MODE && init_count_r ==4'hC) begin
         ddr2_address_init_r <= (`row_address'h0000 | ext_mode_reg);  // OCD EXIT
      end else if(init_state_r1 == INIT_DUMMY_ACTIVE)
        ddr2_address_init_r <= `row_address'h0000;
      else
        ddr2_address_init_r <= `row_address'h0000;
   end
end // always @ (posedge clk0)


always @ (posedge clk0) begin
   if (rst) begin
      ddr2_ba_r[`bank_address-1:0] <= `bank_address'h0;
   end else if (init_memory_r == 1'b1 && init_state_r1 == INIT_LOAD_MODE ) begin
      if (init_count_r == 4'h3) begin
         ddr2_ba_r[`bank_address-1:0] <= `bank_address'h2; //emr2
      end else if (init_count_r == 4'h4) begin
         ddr2_ba_r[`bank_address-1:0] <= `bank_address'h3; //emr3

      end else if (init_count_r == 4'h5 || init_count_r == 4'hB || init_count_r == 4'hC) begin
      
         ddr2_ba_r[`bank_address-1:0] <= `bank_address'h1; //emr
      end else ddr2_ba_r[`bank_address-1:0] <= 2'b00;
 //  end else if ((init_state_r1 == INIT_DUMMY_ACTIVE) || (
  //               (init_state_r1 == INIT_ACTIVE) || (init_state_r1 == INIT_LOAD_MODE) || (init_state_r1 == INIT_PRECHARGE)  )) begin
      end else if (init_state_r1 < INIT_AUTO_REFRESH) begin 
      ddr2_ba_r[`bank_address-1:0] <= 2'b00; 
   end else ddr2_ba_r[`bank_address-1:0] <= ddr2_ba_r[`bank_address-1:0];
end // always @ (posedge clk0)




always @ (posedge clk0) begin
   if (rst) begin
      ddr2_cs_r1[`cs_width-1:0] <= `cs_width'h0;
   end else if (init_memory_r == 1'b1 ) begin
      if (chip_cnt_r == 2'h0) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hE; 
      end else if (chip_cnt_r == 2'h1) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hD; 
      end else if (chip_cnt_r == 2'h2) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hB; 
      end else if (chip_cnt_r == 2'h3) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'h7; 
      end else
        ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hF;            	
   end 
end // always @ (posedge clk0)


//assign ddr2_cke_r = (done_200us == 1'b1) ? `cke_width'hF :  `cke_width'h0 ;

 always @ (posedge clk0) begin
   if (rst) begin
       ddr2_cke_r<= `cke_width'h0;
   end else begin
      if(done_200us_r == 1'b1)
	ddr2_cke_r<= `cke_width'hF;
   end
end


assign phy_init_address[`row_address-1:0]  = ddr2_address_init_r[`row_address-1:0];
assign phy_init_ba [`bank_address-1:0]     = ddr2_ba_r[`bank_address-1:0];     
assign phy_init_ras_n = ddr2_ras_r1;  
assign phy_init_cas_n = ddr2_cas_r1;  
assign phy_init_we_n  = ddr2_we_r1;   
//assign phy_init_cs_n = ddr2_cs_r1;  
   assign phy_init_cs_n = 2'd0;
                             
assign phy_init_cke  = ddr2_cke_r;
  


endmodule // ddr2_controller_0