mem_phy_init.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

//`define simulation  

module mem_phy_init(
		     
input          clk0,
input          rst,
input          first_calib_done,
input          second_calib_done,      
input          ctrl_ref_flag,

		     
output               reg     phy_init_wdf_rden,
output                    phy_init_dqs_rst,
output                    phy_init_dqs_en,
output                    phy_init_wren,
output                    phy_init_rden,
output[`row_address-1:0]  phy_init_address,
output[`bank_address-1:0] phy_init_ba,
output                    phy_init_ras_n,
output                    phy_init_cas_n,
output                    phy_init_we_n,
output [`cs_width-1:0]    phy_init_cs_n,
output [`cke_width-1:0]   phy_init_cke,
output                    phy_init_st1_read,
output                    phy_init_st2_read,
output                    phy_init_initialization_done

                   );

// internal signals
reg [3:0]      init_count_r;
reg            init_memory_r;
reg [7:0]      count_200_cycle_r;
reg [4:0]      init_next_state;
reg [4:0]      init_state_r;
reg [4:0]      init_state_r1;
reg [4:0]      init_state_r2;
reg [`row_address -1:0]     ddr2_address_init_r;  
reg [`bank_address-1:0]     ddr2_ba_r;
reg [5:0]      rfc_count_r;
reg [2:0]      cas_count_r;   
reg [3:0]      cas_check_count_r;
reg [2:0]      wrburst_cnt_r;
reg [2:0]      read_burst_cnt_r;
reg [2:0]      rdburst_cnt_r;   
reg            ddr2_ras_r1;
reg            ddr2_cas_r1;
reg            ddr2_we_r1; 
reg            ddr2_ras_r;
reg            ddr2_cas_r;
reg            ddr2_we_r; 
reg[3:0]       idle_cnt_r;
reg 		dqs_reset;
reg 		dqs_en;
reg [`cs_width-1:0]      ddr2_cs_r2;  
reg [`cs_width-1:0]      ddr2_cs_r1;  
reg [`cs_width-1:0]      ddr2_cs_r;
reg [`cke_width-1:0]    ddr2_cke_r;
reg [1:0]      chip_cnt_r;  
reg 	     count_200cycle_done_r;   
wire[2:0]    burst_cnt;
reg          ctrl_write_en;
reg 	     ctrl_read_en;
wire   [2:0]    CAS_LATENCY_VALUE;
wire   [2:0] 	  BURST_LENGTH_VALUE;
wire   [2:0] 	  ADDITIVE_LATENCY_VALUE;
wire 	        ODT_ENABLE;
wire   		REGISTERED_VALUE;   
wire            ECC_VALUE; 
wire [3:0]     zeroes;   
reg  [4:0]cke_200us_cnt_r;
reg done_200us_r;
reg initalization_done_r;
wire [14:0] load_mode_reg;
wire [14:0] ext_mode_reg;
reg [2:0] ctrl_wren_cnt_r;

   reg 	  wdf_rden_r;
   reg    wdf_rden_r1;
   reg    wdf_rden_r2;
   reg    wdf_rden_r3;
   reg    wdf_rden_r4;
   reg    wdf_rden_r5;
   reg    wdf_rden_r6;
   reg    wdf_rden_r7;
   reg    wdf_rden_r8;
   reg    wdf_rden_r9;
   
   

   





localparam  INIT_ACTIVE              =     5'h00;
localparam  INIT_DUMMY_ACTIVE        =     5'h01;
localparam  INIT_PRECHARGE           =     5'h02;
localparam  INIT_LOAD_MODE           =     5'h03;
localparam  INIT_AUTO_REFRESH        =     5'h04;
localparam  INIT_FIRST_WRITE         =     5'h05;
localparam  INIT_PATTERN_WRITE       =     5'h06;
localparam  INIT_FIRST_READ          =     5'h07;
localparam  INIT_PATTERN_READ        =     5'h08;
localparam  INIT_COUNT_200           =     5'h09;
localparam  INIT_DEEP_MEMORY_ST      =     5'h0A;   
localparam  INIT_MODE_REGISTER_WAIT  =     5'h0B;     
localparam  INIT_PRECHARGE_WAIT      =     5'h0C;
localparam  INIT_AUTO_REFRESH_WAIT   =     5'h0D;
localparam  INIT_COUNT_200_WAIT      =     5'h0E;
localparam  INIT_DUMMY_ACTIVE_WAIT   =     5'h0F;
localparam  INIT_ACTIVE_WAIT         =     5'h10;
localparam  INIT_PATTERN_WRITE_READ  =     5'h11;
localparam  INIT_PATTERN_READ_WAIT   =     5'h12;
localparam  INIT_FIRST_WRITE_READ    =     5'h13;
localparam  INIT_FIRST_READ_WAIT     =     5'h14;
localparam  INIT_IDLE                =     5'h15;
   

assign    phy_init_st1_read = (init_state_r2  == INIT_FIRST_READ) || (init_state_r2 == INIT_FIRST_READ_WAIT);
assign    phy_init_st2_read = ((init_state_r2  == INIT_PATTERN_READ) || (init_state_r2  == INIT_PATTERN_READ_WAIT));
assign    REGISTERED_VALUE = `registered; 
assign    CAS_LATENCY_VALUE = load_mode_reg[6:4];
assign    BURST_LENGTH_VALUE = load_mode_reg[2:0];
assign    ADDITIVE_LATENCY_VALUE = ext_mode_reg[5:3];
assign    ODT_ENABLE = ext_mode_reg[2] | ext_mode_reg[6];
assign    burst_length = burst_cnt;
assign    zeroes = 4'b0000;
assign    ECC_VALUE=	`ecc_enable;
assign    load_mode_reg         = `load_mode_register;
assign    ext_mode_reg         = `ext_load_mode_register;
assign    phy_init_initialization_done =  initalization_done_r; 

assign burst_cnt           = (BURST_LENGTH_VALUE == 3'b010) ? 3'b010 :
                             (BURST_LENGTH_VALUE == 3'b011) ? 3'b100 : 3'b000;
  
   

//to initialize memory
always @ (posedge clk0) begin
   if ((rst)|| (init_state_r == INIT_DEEP_MEMORY_ST))
        init_memory_r <= 1'b1;
   else if (init_count_r == 4'hE)
        init_memory_r <= 1'b0;
end
      
// rfc count
always @ ( posedge clk0) begin
   if (rst)
       rfc_count_r <= 6'b000000;
  // else if ((init_state_r == INIT_ACTIVE)|| (init_state_r ==INIT_LOAD_MODE )|| (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_AUTO_REFRESH)
 //|| (init_state_r == INIT_DUMMY_ACTIVE) || (init_state_r == INIT_ACTIVE) || (init_state_r == INIT_PATTERN_WRITE)|| (init_state_r == INIT_PATTERN_READ)
//|| (init_state_r == INIT_FIRST_WRITE)|| (init_state_r == INIT_FIRST_READ))
    else if((init_state_r < INIT_COUNT_200))
       rfc_count_r <= `rfc_count_value;
   else if (rfc_count_r > 6'd0) 
       rfc_count_r <= rfc_count_r[5:0] - 1;
end


//200us counter for cke 
always @ (posedge clk0) 
begin
  if (rst ) 
     `ifdef simulation
         cke_200us_cnt_r <= 5'b00001;
      //   cke_200us_cnt_r <= 5'b11111;
     `else
         cke_200us_cnt_r <= 5'b11010;
     `endif
  else if (ctrl_ref_flag) 
    cke_200us_cnt_r  <=  cke_200us_cnt_r - 1;   
end


// refresh detect in 266 MHz clock
always @ (posedge clk0) begin
   if (rst) 
      done_200us_r <= 1'b0;
   else  if (done_200us_r == 1'b0)
     done_200us_r <= (cke_200us_cnt_r == 5'b00000);
end

        
// 200 clocks counter - count value : C8
// required for initialization
always @ (posedge clk0) begin
   if (rst)
       count_200_cycle_r <= 8'h00;
   else if (init_state_r == INIT_COUNT_200) 
       count_200_cycle_r <= 8'hC8;
   else if (count_200_cycle_r >8'h00) 
       count_200_cycle_r <= count_200_cycle_r - 1;
end

always @ (posedge clk0) begin
   if (rst) 
       count_200cycle_done_r<= 1'b0;
   else if (init_memory_r && (count_200_cycle_r == 8'h00)) 
       count_200cycle_done_r<= 1'b1;
   else
       count_200cycle_done_r<= 1'b0;
end      

                               
always @ (posedge clk0) begin
  if ((rst)|| (init_state_r == INIT_DEEP_MEMORY_ST)) 
     init_count_r <= 4'd0;
  else if (init_memory_r ) begin
     if (init_state_r == INIT_LOAD_MODE || init_state_r == INIT_PRECHARGE || init_state_r == INIT_AUTO_REFRESH || 
         init_state_r == INIT_COUNT_200 || init_state_r == INIT_DEEP_MEMORY_ST) begin
        init_count_r <= init_count_r + 1'b1;
     end else if(init_count_r == 4'hF ) 
        init_count_r <= 4'd0;   
  end
   
end // always @ (posedge clk0)


always @ (posedge clk0 ) begin
   if (rst) 
        chip_cnt_r <= 2'd0;
   else if ( init_state_r == INIT_DEEP_MEMORY_ST) 
      chip_cnt_r <= chip_cnt_r + 2'd1;
end

// write burst count
always @ (posedge clk0) begin
   if (rst)
       wrburst_cnt_r <= 3'd0;
   else if (init_state_r == INIT_PATTERN_WRITE || init_state_r == INIT_FIRST_WRITE ) 
       wrburst_cnt_r <= burst_cnt;
   else if (wrburst_cnt_r > 3'd0) 
       wrburst_cnt_r <= wrburst_cnt_r - 1'b1;
end

// read burst count for state machine 
always @ (posedge clk0) begin
   if (rst) 
       read_burst_cnt_r <= 3'd0;
   else if (init_state_r == INIT_PATTERN_READ || init_state_r == INIT_FIRST_READ) 
       read_burst_cnt_r <= burst_cnt;
   else if (read_burst_cnt_r > 3'd0) 
       read_burst_cnt_r <= read_burst_cnt_r - 1'b1;
end

// count to generate write enable to the data path
always @ (posedge clk0) begin
   if (rst) 
       ctrl_wren_cnt_r <= 3'd0;
   else if ((init_state_r1 == INIT_FIRST_WRITE)  || (init_state_r1 == INIT_PATTERN_WRITE))
       ctrl_wren_cnt_r <= burst_cnt;
   else if (ctrl_wren_cnt_r > 3'd0)
       ctrl_wren_cnt_r <= ctrl_wren_cnt_r -1'b1;
end

//write enable to data path
always @ (*) begin
     if (ctrl_wren_cnt_r != 3'd0)
        ctrl_write_en <= 1'b1;
     else
       ctrl_write_en <= 1'b0;
end


   assign phy_init_wren = ctrl_write_en;
   


// DQS enable to data path

always @ (*) begin
   
   if ((init_state_r == INIT_PATTERN_WRITE) || (init_state_r == INIT_FIRST_WRITE))
     dqs_reset <= 1'b1;
   else
     dqs_reset <= 1'b0;
end

assign phy_init_dqs_rst = dqs_reset;
   


always @ (*) begin

   if ((init_state_r == INIT_PATTERN_WRITE) || (init_state_r == INIT_FIRST_WRITE) || (wrburst_cnt_r != 3'b000))
     dqs_en <= 1'b1;
   else
     dqs_en <= 1'b0;
end

   assign phy_init_dqs_en = dqs_en;
   
   


// cas count
always @ (posedge clk0) begin
   if (rst)
      cas_count_r <= 3'd0;
   else if (init_state_r == INIT_PATTERN_READ) 
      cas_count_r <= CAS_LATENCY_VALUE + `registered;
   else if (cas_count_r > 3'd0)
      cas_count_r <= cas_count_r - 1;
end

always @ (posedge clk0) begin
   if (rst) 
       cas_check_count_r <= 4'd0;
   else if ((init_state_r1 == INIT_PATTERN_READ) )
          cas_check_count_r <= (CAS_LATENCY_VALUE - 1);
   else if (cas_check_count_r > 4'd0)