mem_phy_write.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////


module mem_phy_write (    input          CLK,
   input          CLK90,
   input          RESET0,
   input          RESET90,
   input [(`data_width*2)-1:0]   WDF_DATA,
   input [(`data_mask_width*2)-1:0]   MASK_DATA,
   input          ctrl_wren,
   input          ctrl_dqs_rst,
   input          ctrl_dqs_en,
   input          phy_init_dqs_rst,
   input          phy_init_dqs_en,
   input          phy_init_wren,
   input          phy_init_initialization_done,
			  
   output         dqs_rst,
   output         dqs_en,
   output         wr_en,
   output [`data_width-1:0]  wr_data_rise,
   output [`data_width-1:0]  wr_data_fall,
   output [`data_mask_width-1:0]   mask_data_rise, 
   output [`data_mask_width-1:0]   mask_data_fall 

                     
                     );
                     
            


   reg wr_en_clk270_r1;
   
   reg wr_en_clk90_r3;
   
   reg dqs_rst_r1;
   reg dqs_rst_r2;
 
   reg dqs_en_r1;
   reg dqs_en_r2;
   reg dqs_en_r3;
 reg [`data_width-1:0]dummy_rise_pattern;   
 reg [`data_width-1:0]dummy_fall_pattern;   
 reg     dummy_flag;
   reg 	 dummy_flag0;
   reg   dummy_flag1_0;

   reg [2:0] dummy_wr_cnt_r;
   
   
   
  reg CTRL_DUMMY_WR_SEL_270;
  reg CTRL_DUMMY_WR_SEL_90;
  reg CTRL_DUMMY_WR_SEL_r1;

wire [143:0] patA;
wire [143:0] pat5;
wire [143:0] pat9;
wire [143:0] pat6;

wire   [2:0]    CAS_LATENCY_VALUE;
wire   [2:0] 	  ADDITIVE_LATENCY_VALUE;
wire   		REGISTERED_VALUE;   
wire            ECC_VALUE; 


   wire [143:0] pat0, pat1;


   reg [9:3] 	dqs_en_stages_r;
   reg [9:3] 	dqs_rst_stages_r;
   reg [9:3] 	wr_en_stages_r;

   wire [14:0] load_mode_reg;
wire [14:0] ext_mode_reg;




   
   
  
  

assign  dqs_rst = dqs_rst_r2; 
assign  dqs_en = dqs_en_r3; 
assign  wr_en =wr_en_clk90_r3;

assign    load_mode_reg         = `load_mode_register;
assign    ext_mode_reg         = `ext_load_mode_register;



assign    REGISTERED_VALUE = `registered; 
assign    CAS_LATENCY_VALUE = load_mode_reg[6:4];
assign    ADDITIVE_LATENCY_VALUE = ext_mode_reg[5:3];
assign    ECC_VALUE=	`ecc_enable;   
/*
 generate
   genvar dqs_i;
     for (dqs_i = 3; dqs_i<9; dqs_i=dqs_i+1)
       begin: dqs_enn
	   always@(posedge CLK)begin
	     if(RESET0)
             begin
                dqs_en_stages_r[9:4] <= 6'd0;
		dqs_rst_stages_r[9:4]<= 6'd0;
		wr_en_stages_r[9:4]  <= 6'd0;
             end
            else
              begin
                dqs_en_stages_r[dqs_i + 1] <= dqs_en_stages_r[dqs_i];		
                dqs_rst_stages_r[dqs_i + 1] <= dqs_rst_stages_r[dqs_i];		
               wr_en_stages_r[dqs_i + 1] <= wr_en_stages_r[dqs_i];
              end // else: !if(RESET0)
           end // always@ (posedge CLK)
end // block: dqs_en
endgenerate
*/

	   always@(posedge CLK)begin
	     if(RESET0)
             begin
                dqs_en_stages_r <= 7'd0;
		dqs_rst_stages_r <= 7'd0;
		wr_en_stages_r  <= 7'd0;
             end
            else
              begin
				  
               dqs_en_stages_r[3] <= ctrl_dqs_en | phy_init_dqs_en;
	       dqs_en_stages_r[4] <= dqs_en_stages_r[3];
	       dqs_en_stages_r[5] <= dqs_en_stages_r[4];
               dqs_en_stages_r[6] <= dqs_en_stages_r[5];
               dqs_en_stages_r[7] <= dqs_en_stages_r[6];
               dqs_en_stages_r[8] <= dqs_en_stages_r[7];
               dqs_en_stages_r[9] <= dqs_en_stages_r[8];	 
	       dqs_rst_stages_r[3] <= ctrl_dqs_rst | phy_init_dqs_rst;
	       dqs_rst_stages_r[4] <= dqs_rst_stages_r[3];
	       dqs_rst_stages_r[5] <= dqs_rst_stages_r[4];
               dqs_rst_stages_r[6] <= dqs_rst_stages_r[5];
               dqs_rst_stages_r[7] <= dqs_rst_stages_r[6];
               dqs_rst_stages_r[8] <= dqs_rst_stages_r[7];
               dqs_rst_stages_r[9] <= dqs_rst_stages_r[8];	 
	       wr_en_stages_r[3] <= ctrl_wren | phy_init_wren;
	       wr_en_stages_r[4] <= wr_en_stages_r[3];
	       wr_en_stages_r[5] <= wr_en_stages_r[4];
               wr_en_stages_r[6] <= wr_en_stages_r[5];
               wr_en_stages_r[7] <= wr_en_stages_r[6];
               wr_en_stages_r[8] <= wr_en_stages_r[7];
               wr_en_stages_r[9] <= wr_en_stages_r[8];
               	 
		 
	      end // else: !if(RESET0)
	   end // always@ (posedge CLK)
   
   

  
  always @ (negedge CLK90)
   begin
     if (RESET0 == 1'b1)
       begin
         wr_en_clk270_r1 <= 1'b0;
         dqs_rst_r1      <= 1'b0;
         dqs_en_r1       <= 1'b0; 
       end
     else                         
       begin                      
         wr_en_clk270_r1  <= wr_en_stages_r[ADDITIVE_LATENCY_VALUE + CAS_LATENCY_VALUE  + REGISTERED_VALUE  + ECC_VALUE];
         dqs_rst_r1       <= dqs_rst_stages_r[ADDITIVE_LATENCY_VALUE + CAS_LATENCY_VALUE  + REGISTERED_VALUE  + ECC_VALUE];
         dqs_en_r1        <= ~dqs_en_stages_r[ADDITIVE_LATENCY_VALUE + CAS_LATENCY_VALUE  + REGISTERED_VALUE  + ECC_VALUE];
       end // else: !if(RESET0 == 1'b1)
   end // always @ (negedge CLK90)
   
   always @ (negedge CLK)
   begin
     if (RESET0 == 1'b1)
       begin
         dqs_rst_r2        <= 1'b0;
         dqs_en_r2         <= 1'b0;
         dqs_en_r3         <= 1'b0;
       end
     else
       begin
         dqs_rst_r2        <= dqs_rst_r1;
         dqs_en_r2         <= dqs_en_r1;
         dqs_en_r3         <= dqs_en_r2;
       end // else: !if(RESET0 == 1'b1)
   end // always @ (negedge CLK)
   
  always @ (posedge CLK90)
   begin
     if (RESET90 == 1'b1)
       begin
         wr_en_clk90_r3      <= 1'b0;
       end
     else                    
       begin
         wr_en_clk90_r3      <= wr_en_clk270_r1;                           
         
       end // else: !if(RESET90 == 1'b1)
   end // always @ (posedge CLK90)
         



 assign wr_data_rise = WDF_DATA[(`data_width*2)-1:`data_width];
 assign wr_data_fall = WDF_DATA[`data_width-1:0]; 
       	


assign mask_data_rise = MASK_DATA[(`data_mask_width*2)-1:`data_mask_width];
assign mask_data_fall = MASK_DATA[`data_mask_width-1:0];	 



endmodule // mem_phy_write