mem_phy_dqs_iob.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

module mem_phy_dqs_iob (   
   input        CLK,
   input        CLK90,       
   input        RESET,
   input        DLYINC,
   input        DLYCE,
   input        DLYRST,
   input        CTRL_DQS_RST,
   input        CTRL_DQS_EN,
   inout        DDR_DQS,
   inout        DDR_DQS_L,
   output       DQS_RISE               
                    );





   wire         dqs_in;
   wire         dqs_out;
   wire         dqs_out_l;
   wire         dqs_delayed;
   wire         dqs_delayed_o;
   wire         ctrl_dqs_en_r1;
   wire         vcc;
   wire         gnd;
   wire         clk180;
   reg          data1;
   reg          data2;
   
   assign vcc         = 1'b1;
   assign gnd         = 1'b0;
   assign clk180      = ~CLK;   
//   assign RESET = 1'b0;
// synthesis attribute max_fanout of data1 is 1
// synthesis attribute max_fanout of data2 is 1

always @ (posedge clk180)
begin
  if (CTRL_DQS_RST == 1'b1)
    data1 <= 1'b0;
  else
    data1 <= 1'b1;
end

always @ (posedge clk180)
begin
  if (CTRL_DQS_RST == 1'b1)
    data2 <= 1'b1;
  else
    data2 <= 1'b0;
end


   assign DQS_RISE = dqs_delayed_o;
   
   


defparam idelay_dqs.IOBDELAY_TYPE = "VARIABLE";
defparam idelay_dqs.IOBDELAY_VALUE = 0;

IDELAY idelay_dqs (
                   .O(dqs_delayed),
                   .I(dqs_in),
                   .C(CLK90),   
                   .CE(DLYCE),
                   .INC(DLYINC),
                   .RST(DLYRST)
                   );
 

 BUFIO bufio1 (.I(dqs_delayed),
              .O(dqs_delayed_o));

                   
defparam oddr_dqs.SRTYPE = "SYNC";
defparam oddr_dqs.DDR_CLK_EDGE = "OPPOSITE_EDGE";

ODDR oddr_dqs (
               .Q(dqs_out),
               .C(clk180),
               .CE(vcc),
               .D1(data1),
               .D2(gnd),
               .R(gnd),
               .S(gnd)
               );
              

defparam oddr_dqs_l.SRTYPE = "SYNC";
defparam oddr_dqs_l.DDR_CLK_EDGE = "OPPOSITE_EDGE";

ODDR oddr_dqs_l (
               .Q(dqs_out_l),
               .C(clk180),
               .CE(vcc),
               .D1(data2),
               .D2(vcc),
               .R(gnd),
               .S(gnd)
               );


//defparam tri_state_dqs.IOB = "TRUE";               
FD tri_state_dqs (    .D(CTRL_DQS_EN),
                  .Q(ctrl_dqs_en_r1),
                  .C(clk180)
                  );
                  
                  
IOBUFDS iobuf_dqs (
                   .O(dqs_in), 
                   .IO(DDR_DQS), 
                   .IOB(DDR_DQS_L), 
                   .I(dqs_out),
                   .T(ctrl_dqs_en_r1)
                   );                              
            
                   
endmodule