mem_phy.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

module mem_phy(    input          CLK,
   input          CLK90,
//   input          CAL_CLK,
   input          RESET0,
   input          RESET90,
   input          RESET_CAL_CLK,
   input [(`data_width*2)-1:0]  WDF_DATA,
   input [(`data_mask_width*2)-1:0]   MASK_DATA,
   input          ctrl_wren,
   input          ctrl_dqs_rst,
   input          ctrl_dqs_en,
   input       idelay_ctrl_rdy,
   input[`row_address-1  :0]   ctrl_address,
   input[`bank_address-1 :0]   ctrl_ba,
   input         ctrl_ras_n,
   input         ctrl_cas_n,
   input         ctrl_we_n,
   input   [`cs_width-1:0]      ctrl_cs_n,
   input    [`odt_width-1:0]     ctrl_odt,
   input                         ctrl_rden,
   input                         ctrl_ref_flag,



		   
inout [`data_width-1:0]   DDR_DQ,
inout [`data_strobe_width-1:0]   DDR_DQS,
inout [`data_strobe_width-1:0]   DDR_DQS_L,



   output [43:0]  test_bus,
   output         phy_init_wdf_rden,		   
   output         dqs_rst,
   output         dqs_en,
   output         wr_en,
   output [`data_width-1:0]  wr_data_rise,
   output [`data_width-1:0]  wr_data_fall,

   output [`data_mask_width-1:0] mask_data_rise,
   output [`data_mask_width-1:0] mask_data_fall,
   output [`data_width-1:0] rd_data_rise,
   output [`data_width-1:0] rd_data_fall,
   output [`data_mask_width-1:0]   DDR_DM,
   output                  first_calib_done,
   output                  second_calib_done,
   output [`row_address-1  :0] DDR_ADDRESS,
   output [`bank_address-1 :0] DDR_BA,
   output        DDR_RAS_L,
   output        DDR_CAS_L,
   output        DDR_WE_L,
   output  test_ras_n,
   output  test_cas_n,
   output  test_we_n,
   output    [`cke_width-1:0]    DDR_CKE,
   output   [`odt_width-1:0]     DDR_ODT,
   output  [`cs_width-1:0]      ddr_cs_L,
   output                       phy_init_initialization_done,
   output  [`data_strobe_width-1:0]                     phy_calib_rden );


   wire 			phy_init_dqs_rst;   
   wire 			phy_init_dqs_en;   
   wire 			phy_init_wren;   
   wire 			phy_init_rden;   
   wire [`row_address-1:0] 	phy_init_address;   
   wire [`bank_address-1:0] 	phy_init_ba;   
   wire 			phy_init_ras_n;   
   wire 			phy_init_cas_n;   
   wire 			phy_init_we_n;   
   wire [`cs_width-1:0] 	phy_init_cs_n; 
   wire [`cke_width-1:0] 	phy_init_cke; 
   wire 			phy_init_st1_read;  
   wire 			phy_init_st2_read;  
   wire                         phy_init_initialization_done_w;
   
                     
   assign 					phy_init_initialization_done = phy_init_initialization_done_w;
   
  
mem_phy_write  mem_phy_write
		   (
                     .CLK			(CLK),
                     .CLK90			(CLK90),
                     .RESET0			(RESET0),
                     .RESET90			(RESET90),
                     .WDF_DATA		        (WDF_DATA),
                     .MASK_DATA		        (MASK_DATA),
                     .ctrl_wren		        (ctrl_wren),
                     .ctrl_dqs_rst		(ctrl_dqs_rst),
                     .ctrl_dqs_en		(ctrl_dqs_en),
                     .dqs_rst			(dqs_rst),
                     .dqs_en			(dqs_en),

		     .phy_init_dqs_rst(phy_init_dqs_rst),
		     .phy_init_dqs_en(phy_init_dqs_en),
		     .phy_init_wren(phy_init_wren),
		     .phy_init_initialization_done(phy_init_initialization_done_w),
                     .wr_en			(wr_en),
                     .wr_data_rise		(wr_data_rise),
                     .wr_data_fall		(wr_data_fall),
                     .mask_data_rise	(mask_data_rise),
                     .mask_data_fall	(mask_data_fall)
                     
                     );



  mem_phy_io data_path_iobs_00(
                     .CLK(CLK),
                     .CLK90(CLK90),
//                     .CAL_CLK(CAL_CLK),
                     .RESET0(RESET0),
                     .RESET90(RESET90),
                     .idelay_ctrl_rdy(idelay_ctrl_rdy),



		     .phy_init_rden(phy_init_rden),
		     .phy_init_initialization_done(phy_init_initialization_done_w),
		     .phy_init_st1_read(phy_init_st1_read),
		     .phy_init_st2_read(phy_init_st2_read),

                     .test_bus(test_bus),
                     .dqs_rst(dqs_rst),
                     .dqs_en(dqs_en),
                     .first_calib_done(first_calib_done),
		     .second_calib_done(second_calib_done),
		     .phy_calib_rden(phy_calib_rden),
		     .ctrl_rden(ctrl_rden),

                     .wr_data_rise(wr_data_rise),
                     .wr_data_fall(wr_data_fall),
                     .wr_en(wr_en),
                     .rd_data_rise(rd_data_rise),
                     .rd_data_fall(rd_data_fall),
                     .mask_data_rise(mask_data_rise),
                     .mask_data_fall(mask_data_fall),
                     .DDR_DQ(DDR_DQ),
                     .DDR_DQS(DDR_DQS),
                     .DDR_DQS_L(DDR_DQS_L),
                     .DDR_DM(DDR_DM)
                     );

mem_phy_ctl_io controller_iobs_00(
                   .clk(CLK),
		   .rst(RESET0),
                   .ctrl_address(ctrl_address),
                   .ctrl_ba(ctrl_ba),
                   .ctrl_ras_n(ctrl_ras_n),
                   .ctrl_cas_n(ctrl_cas_n),
                   .ctrl_we_n(ctrl_we_n),
                   .ctrl_cs_n(ctrl_cs_n),
                   .ctrl_odt(ctrl_odt),
                   .test_ras_n(test_ras_n),
                   .test_cas_n(test_cas_n),
                   .test_we_n(test_we_n),
		   	    .phy_init_address(phy_init_address),
			    .phy_init_ba(phy_init_ba),
			    .phy_init_ras_n(phy_init_ras_n),
			    .phy_init_cas_n(phy_init_cas_n),
			    .phy_init_we_n(phy_init_we_n),
			    .phy_init_cs_n(phy_init_cs_n),
			    .phy_init_cke(phy_init_cke),
		            .phy_init_initialization_done(phy_init_initialization_done_w),

                      .DDR_ADDRESS(DDR_ADDRESS),
                      .DDR_BA(DDR_BA),
                .DDR_RAS_L(DDR_RAS_L),
                .DDR_CAS_L(DDR_CAS_L),
                .DDR_WE_L(DDR_WE_L),
                  .DDR_CKE(DDR_CKE),
                .DDR_ODT(DDR_ODT),
                  .DDR_CS_L(ddr_cs_L)
                   );



 mem_phy_init  mem_phy_init(.clk0(CLK),
                            .rst(RESET0),
			    .first_calib_done(first_calib_done),
			    .second_calib_done(second_calib_done),
			    .ctrl_ref_flag(ctrl_ref_flag),

			    .phy_init_dqs_rst(phy_init_dqs_rst),
			    .phy_init_wdf_rden(phy_init_wdf_rden),
			    .phy_init_dqs_en(phy_init_dqs_en),
			    .phy_init_wren(phy_init_wren),
			    .phy_init_rden(phy_init_rden),
			    .phy_init_address(phy_init_address),
			    .phy_init_ba(phy_init_ba),
			    .phy_init_ras_n(phy_init_ras_n),
			    .phy_init_cas_n(phy_init_cas_n),
			    .phy_init_we_n(phy_init_we_n),
			    .phy_init_cs_n(phy_init_cs_n),
			    .phy_init_cke(phy_init_cke),
			    .phy_init_st1_read(phy_init_st1_read),
			    .phy_init_st2_read(phy_init_st2_read),
			    .phy_init_initialization_done(phy_init_initialization_done_w));
   
             

                        
endmodule