mem_param.v

xilinx公司的ＤＤＲ实现源码

/************************************************9*******************************
**$ID: mem_interface_top_ddr2_controller_0.v 1.10 2005/10/04 23:17:17 karthip Exp karthip $
**$Date: 2006/03/08 18:52:07 $
**$Author: karthip $
**$Revision: 1.6 $
**$Source: /home/karthip/v5/1_19/rtl/RCS/mem_param.v,v $
********************************************************************************/



// counter values in the controller in tCK units 
// write latency (WL) = Read Latency (RL) - 1 = AL + CL -1 
// Read Latency (RL ) = AL + CL 
`timescale 1ns/100ps


`define    data_width                               64
`define    data_strobe_width                        8
`define    data_mask_width                          8
`define    clk_width                                3
`define    fifo16                                   4
`define    cs_width                                 2
`define    odt_width                                2
`define    cke_width                                2
`define    deep_memory                              0
`define    row_address                              14
`define    column_address                           10
`define    bank_address                             2
`define    memory_width                             8
`define    registered                               0
`define    unbuffered                               0
`define    no_of_CS                                 2
`define    RESET                                    0
`define    ecc_enable                               0
`define    ecc_width                                0
`define    load_mode_register       14'b00001001010010
`define    ext_load_mode_register   14'b00000000000000
`define    chip_address                     1
`define    rcd_count_value                 15/`period
`define    ras_count_value                 40/`period
`define    mrd_count_value                 15/`period
`define    rp_count_value                  15/`period
`define    rfc_count_value                 75/`period
`define    trtp_count_value                8/`period
`define    twr_count_value                 15/`period
`define    twtr_count_value                10/`period
`define     max_ref_width                   7
`define    max_ref_cnt                     7700/`period
`define    period                          4


`define    col_range_start                          0
`define    col_range_end                            9
`define    row_range_start                          10
`define    row_range_end                            23
`define    bank_range_start                         24
`define    bank_range_end                           25
`define    cs_range_start                           26
`define    cs_range_end                             27