mem_usr_ip_addr_fifo.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////



module mem_usr_ip_addr_fifo (
input         clk0,
input         rst,
input[35:0]   app_af_addr,  
input         app_af_WrEn,
input         ctrl_af_RdEn,

output[35:0]  af_addr,
output        af_Empty,
output        af_Almost_Full

                   );
                      
wire [35:0]  fifo_input_write_addr;
wire [35:0]  fifo_output_write_addr;

reg [35:0]   compare_value_r ;
reg [35:0]   app_af_addr_r   ;
reg [35:0]   fifo_input_addr_r;
reg          af_en_r;
reg          af_en_2r;
wire         compare_result_row;
wire         compare_result_bank;
   wire [2:0] t1, t2;
   
   

   
   
   
// [35]  -- row conflict;
// [34] -- bank conflict;
// [33:31]  -- command to controller
// [30:0]   --- address

// [34:1] OF THE INPUT ADDRESS IS ASSIGNED. THIS HAS TO BE CHANGED. CHANGE IT BEFORE RELEASING THE CODE. 
assign fifo_input_write_addr[35:0] = {compare_result_row, compare_result_bank, app_af_addr_r[33:0]};
assign af_addr[35:0]              = fifo_output_write_addr;
//assign compare_result              = (compare_value_r[`cs_width + `bank_address + `row_address + `col_ap_width- 1:`col_ap_width] 
//                                   == fifo_input_write_addr[`cs_width + `bank_address + `row_address + `col_ap_width- 1:`col_ap_width]) ? 1'b0: 1'b1;
assign compare_result_row              = (compare_value_r[`row_address + `column_address:`column_address+1] 
                                       == fifo_input_write_addr[`row_address + `column_address:`column_address+1]) ? 1'b0: 1'b1;

   // THIS HAS TO INCLUDE `CS_WIDTH also. MAKE THIS CHANGE BEFORE RELEASING THE COD
assign compare_result_bank              = (compare_value_r[`bank_range_end:`bank_range_start] 
                                   == fifo_input_write_addr[`bank_range_end:`bank_range_start]) ? 1'b0: 1'b1;


   
always@(posedge clk0)
  begin
     if(rst)
       begin
	  compare_value_r         <= 36'd0;
       app_af_addr_r[35:0]    <= 36'd0;
       fifo_input_addr_r[35:0] <= 36'd0;
       af_en_r              <= 1'b0;
       af_en_2r             <= 1'b0;
       end
     else
       begin
       if(af_en_r)
          compare_value_r<= fifo_input_write_addr;
       app_af_addr_r[35:0]    <= app_af_addr[35:0];
       fifo_input_addr_r[35:0] <= fifo_input_write_addr[35:0];
       af_en_r              <= app_af_WrEn;
       af_en_2r             <= af_en_r;       
       end
  end
                               
                            
// Read/Write Address FIFO



defparam af_fifo36.ALMOST_FULL_OFFSET = 12'h080;
defparam af_fifo36.ALMOST_EMPTY_OFFSET = 12'h007;
defparam af_fifo36.DATA_WIDTH = 36;
defparam af_fifo36.DO_REG = 1;
defparam af_fifo36.EN_SYN = "FALSE";
defparam af_fifo36.FIRST_WORD_FALL_THROUGH = "TRUE";


FIFO36  af_fifo36(
           .ALMOSTEMPTY(), 
           .ALMOSTFULL(af_Almost_Full), 
           .DO(fifo_output_write_addr[31:0]), 
           .DOP(fifo_output_write_addr[35:32]), 
           .EMPTY(af_Empty), 
           .FULL(), 
           .RDCOUNT(), 
           .RDERR(), 
           .WRCOUNT(), 
           .WRERR(), 
           .DI(fifo_input_addr_r[31:0]), 
           .DIP(fifo_input_addr_r[35:32]), 
           .RDCLK(clk0), 
           .RDEN(ctrl_af_RdEn), 
           .RST(rst), 
           .WRCLK(clk0), 
           .WREN(af_en_2r)
          );
		

endmodule