mem_ctrl.v

xilinx公司的ＤＤＲ实现源码

   else if (rcd_count_r != 3'd0)
       rcd_count_r <= rcd_count_r - 1'b1;
end

      
// ras count - active to precharge
always @ ( posedge clk0) begin
   if (rst) 
       ras_count_r <= 4'd0;
   else if ((state_r == ACTIVE) )
       ras_count_r <= `ras_count_value;
   else if (ras_count_r > 4'd0)
       ras_count_r <= ras_count_r - 1'b1;
end
      
//AL+BL/2+TRTP-2      
// rtp count - read to precharge
always @ ( posedge clk0) begin
   if (rst) 
       rtp_count_r <= 4'd0;
   else if (state_r == BURST_READ ) 
       rtp_count_r <= (`trtp_count_value + burst_cnt + add_lat -2'd3) ;
   else if(rtp_count_r > 4'd0)
       rtp_count_r <= rtp_count_r - 1'b1;
end



// WL+BL/2+TWR      
// wtp count - write to precharge
always @ ( posedge clk0) begin
   if (rst) 
       wtp_count_r <= 4'd0;
   else if (state_r == BURST_WRITE )
       wtp_count_r <= (`twr_count_value + burst_cnt + cas_lat + add_lat -2'd2)  ;
   else if (wtp_count_r > 4'd0) 
       wtp_count_r <= wtp_count_r - 1'd1;
end


   
// write to read counter 
// write to read includes : write latency + burst time + tWTR
      
always @ (posedge clk0) begin
   if (rst)
       wr_to_rd_count_r <= 4'd0;
   else if (state_r == BURST_WRITE  )
       wr_to_rd_count_r <= (`twtr_count_value + burst_cnt + add_lat + cas_lat - 2'd2);
   else if (wr_to_rd_count_r >  4'd0)
       wr_to_rd_count_r <= wr_to_rd_count_r - 1'd1;
end

// read to write counter
always @ (posedge clk0) begin
   if (rst)
      rd_to_wr_count_r<= 4'd0;
   else if ((state_r == BURST_READ)  )
      rd_to_wr_count_r <= ( add_lat + `registered + burst_cnt );
   else if (rd_to_wr_count_r >4'd0)
      rd_to_wr_count_r <= rd_to_wr_count_r - 1'd1;
end
       

// auto refresh interval counter in refresh_clk domain
always @ (posedge clk0) begin
   if (rst) 
      refi_count_r <= 12'd0;
   else if (refi_count_r == `max_ref_cnt )
      refi_count_r <= 12'd0;
   else
      refi_count_r <= refi_count_r + 1'd1;
    
end

assign ref_flag = ((refi_count_r == `max_ref_cnt)) ? 1'b1 : 1'b0;

assign ctrl_ref_flag = (refi_count_r == `max_ref_cnt);
   
 
//refresh flag detect
//auto_ref high indicates auto_refresh requirement
//auto_ref is held high until auto refresh command is issued.
always @(posedge clk0) begin
    if (rst)
       auto_ref_r <= 1'b0;
    else if (ref_flag && phy_init_initialization_done)
       auto_ref_r <= 1'b1;
    else if (state_r == AUTO_REFRESH)
       auto_ref_r <= 1'b0;
end
        
                            
assign burst_cnt           = (brst_lnth == 3'b010) ? 3'b010 :
                             (brst_lnth == 3'b011) ? 3'b100 : 3'b000;

                                    

always @ (posedge clk0 ) begin
   if (rst || (state_r == PRECHARGE ))
        auto_cnt_r <= 3'd0;
   else if ( state_r ==AUTO_REFRESH)
     auto_cnt_r <= auto_cnt_r + 1'b1;
end   

// write burst count
always @ (posedge clk0) begin
   if (rst)
       wrburst_cnt_r<= 3'd0;
   else if (state_r == BURST_WRITE )
       wrburst_cnt_r <= burst_cnt;
   else if (wrburst_cnt_r > 3'd0)
       wrburst_cnt_r <= wrburst_cnt_r - 1'd1;
end

// read burst count for state machine 
always @ (posedge clk0) begin
   if (rst)
       read_burst_cnt_r<= 3'd0;
   else if (state_r == BURST_READ)
       read_burst_cnt_r<= burst_cnt;
    else if (read_burst_cnt_r > 3'd0)
       read_burst_cnt_r<= read_burst_cnt_r - 1'd1;
end

// count to generate write enable to the data path
always @ (posedge clk0) begin
   if (rst)
       ctrl_wren_cnt_r <= 3'd0;
   else if (wdf_rden_r) 
       ctrl_wren_cnt_r <= burst_cnt;
   else if (ctrl_wren_cnt_r > 3'd0) 
       ctrl_wren_cnt_r <= ctrl_wren_cnt_r  -1'd1;
end

//write enable to data path
always @ (*) begin
     if (ctrl_wren_cnt_r  != 3'd0)
        ctrl_write_en <= 1'b1;
     else
       ctrl_write_en <= 1'b0;
end

assign ctrl_wren = ctrl_write_en;
    


always @ (*) begin
   
   if (((state_r == BURST_WRITE) && ~burst_write_r))
     dqs_reset <= 1'b1;
   else
     dqs_reset <= 1'b0;
end

   assign ctrl_dqs_rst = dqs_reset;
   
   

always @ (*) begin

   if ((state_r == BURST_WRITE) || (wrburst_cnt_r != 3'd0))
     dqs_en <= 1'b1;
   else
     dqs_en <= 1'b0;
end
   
   assign ctrl_dqs_en = dqs_en;
  


// cas count
always @ (posedge clk0) begin
   if (rst)
      cas_count_r<= 3'd0;
   else if (((state_r == BURST_READ) && ~burst_read_r) ) 
      cas_count_r  <= cas_lat + `registered;
   else if (cas_count_r != 3'd0) 
      cas_count_r <= cas_count_r - 1'b1;
end



always @ (posedge clk0) begin
   if (rst)
       cas_check_count_r <= 4'd0;
   else if ((state_r1 == BURST_READ) && ~burst_read_r1)
          cas_check_count_r <= (cas_lat - 1'b1);
   else if (cas_check_count_r > 4'd0)
       cas_check_count_r <= cas_check_count_r - 1'd1;
   else
     cas_check_count_r <= 4'd1;
end

always @ (posedge clk0) begin
   if (rst) 
      rdburst_cnt_r  <= 3'd0;    
   else if((state_r2 == BURST_READ) && burst_read_r2) begin
      if(burst_cnt[2])
	rdburst_cnt_r <= (({burst_cnt[2:0],1'b0})-(3'd7 - cas_lat));
      else 
	rdburst_cnt_r<= (({burst_cnt[2:0],1'b0}) -(3'd5 - cas_lat));
   end else if ((cas_check_count_r == 4'b0010))
      rdburst_cnt_r <= burst_cnt;  
   else if (rdburst_cnt_r > 3'd0)                  
      rdburst_cnt_r <= rdburst_cnt_r - 1'b1;
end // always @ (posedge clk0)


//read enable to data path
always @ (rdburst_cnt_r) begin
   if ((rdburst_cnt_r == 3'd0)) begin
      ctrl_read_en <= 1'b0;
   end else begin
      ctrl_read_en <= 1'b1;
   end
end


 assign ctrl_rden = ctrl_read_en;


 assign af_rden = (state_r ==BURST_WRITE || state_r ==BURST_READ);
   


// write data fifo read enable
always @ (posedge clk0) begin
   if (rst) 
       wdf_rden_r  <= 1'b0;
   else if ((state_r ==BURST_WRITE))  // place holder for burst_write
       wdf_rden_r  <= 1'b1;
   else 
     wdf_rden_r  <= 1'b0;
end

always @ (posedge clk0) begin
   if (rst) 
     begin
       wdf_rden_r2 <= 1'b0;
       wdf_rden_r3 <= 1'b0;
       wdf_rden_r4 <= 1'b0;
     end
   else 
     begin
       wdf_rden_r2 <= wdf_rden_r;
       wdf_rden_r3 <= wdf_rden_r2;
       wdf_rden_r4 <= wdf_rden_r3;
     end // else: !if(rst)
end // always @ (posedge clk0)
   


// Read enable to the data fifo

always @ (*) begin
   if (burst_cnt == 3'b010) begin
       ctrl_wdf_read_en<= (wdf_rden_r | wdf_rden_r2) ;
   end else if (burst_cnt == 3'b100)
       ctrl_wdf_read_en<= (wdf_rden_r | wdf_rden_r2 | wdf_rden_r3 | wdf_rden_r4) ;
   else ctrl_wdf_read_en<= 1'b0;
   
end

   always @(posedge clk0) begin 
   if (rst) begin
       ctrl_wdf_rden <= 1'b0;
       ctrl_wdf_read_en_r1<= 1'b0;
       ctrl_wdf_read_en_r2<= 1'b0;
       ctrl_wdf_read_en_r3<= 1'b0;
       ctrl_wdf_read_en_r4<= 1'b0;
       ctrl_wdf_read_en_r5<= 1'b0;
       ctrl_wdf_read_en_r6<= 1'b0;
   end else begin

   ctrl_wdf_read_en_r1<= ctrl_wdf_read_en;
   ctrl_wdf_read_en_r2<= ctrl_wdf_read_en_r1;
   ctrl_wdf_read_en_r3<= ctrl_wdf_read_en_r2;
   ctrl_wdf_read_en_r4<= ctrl_wdf_read_en_r3;
   ctrl_wdf_read_en_r5<= ctrl_wdf_read_en_r4;
   ctrl_wdf_read_en_r6<= ctrl_wdf_read_en_r5;
   case(add_lat + cas_lat + reg_val)
       4'b0011: ctrl_wdf_rden  <= ctrl_wdf_read_en;
       4'b0100: ctrl_wdf_rden  <= ctrl_wdf_read_en_r1;
       4'b0101: ctrl_wdf_rden  <= ctrl_wdf_read_en_r2;
       4'b0110: ctrl_wdf_rden  <= ctrl_wdf_read_en_r3;
       4'b0111: ctrl_wdf_rden  <= ctrl_wdf_read_en_r4;
       4'b1000: ctrl_wdf_rden  <= ctrl_wdf_read_en_r5;
       4'b1001: ctrl_wdf_rden  <= ctrl_wdf_read_en_r6;
   default: ctrl_wdf_rden  <= 1'b0;
   endcase // case(ADDITIVE_LATENCY_VALUE + CAS_LATENCY_VALUE )
   end // else: !if(rst)
end // always @ (posedge clk0)


always @ (posedge clk0) begin
  if (rst ) begin
     phy_init_initialization_done_r <= 1'd0;
  end else begin
     phy_init_initialization_done_r <= phy_init_initialization_done;
  end
end

always @ (posedge clk0) begin
  if (rst) begin
      state_r <= IDLE;
  end else begin
     if(phy_init_initialization_done_r)
        state_r <= next_state;
  end
end

  
// main control state machine  
always @ (*) 
 begin
	  
   next_state = state_r;
    burst_read = 1'd0;
    burst_write = 1'd0;
    
   case (state_r)
    
     IDLE : begin
	      if(auto_ref_r)
		next_state = PRECHARGE;
	      else if ((WR_r  || RD_r  )) 
                next_state = ACTIVE;	   
            end 
     
     PRECHARGE          : begin 
                         if(auto_ref_r)
			    next_state = PRECHARGE_WAIT1;
	                 else 
                             next_state = PRECHARGE_WAIT;
     end
                   
     PRECHARGE_WAIT     : begin
        if (rp_count_r == 3'b000) begin
           if (auto_ref_r ) begin
                next_state = PRECHARGE; // precharge again to close all the banks 
           end else  begin
              next_state = ACTIVE;
           end
	end
     end // case: PRECHARGE_WAIT

     PRECHARGE_WAIT1: if(rp_count_r == 3'b000) next_state = AUTO_REFRESH;

         
     AUTO_REFRESH       : next_state = AUTO_REFRESH_WAIT;
  
  
     AUTO_REFRESH_WAIT  : if(rfc_count_r == 3'd0) next_state = ACTIVE;
	

                         
     ACTIVE             :next_state = ACTIVE_WAIT;
                           
     ACTIVE_WAIT        :if(rcd_count_r == 3'd0) next_state = COMMAND_WAIT;

     COMMAND_WAIT       : begin