mem_test.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////


`define idle  3'b000
`define write 3'b001
`define read  3'b010

module mem_test (
   input         CLK,
   input         RESET,
   input         WDF_ALMOST_FULL,
   input         AF_ALMOST_FULL,
   input [2:0]   BURST_LENGTH,
   input         READ_DATA_VALID,
   input [(`data_width*2)-1:0]  READ_DATA_FIFO_OUT,
   input          phy_init_initialization_done,

		 output [63:0] test_cmp,
   output [35:0] APP_AF_ADDR,
   output        APP_AF_WREN,
   output [(`data_width*2)-1:0] APP_WDF_DATA,
   output [(`data_mask_width*2)-1:0] APP_MASK_DATA,
   output        APP_WDF_WREN,
   output        ERROR

                   );


   
   reg [2:0]     state;
   reg [2:0]     burst_count;
   reg           write_data_en;
   reg           write_addr_en;
   reg [3:0] 	 state_cnt;
   
   
   
   wire [(`data_width*2)-1:0]   app_cmp_data;
   wire [2:0]    burst_len;
   
   assign burst_len = BURST_LENGTH;
   
   
// State Machine for writing to WRITE DATA & ADDRESS FIFOs   
   always @ (posedge CLK)
   begin
     if (RESET == 1'b1)   // State Machine in IDLE state
       begin
         write_data_en <= 1'b0;
         write_addr_en <= 1'b0;
         state[2:0]     <= `idle;
	 state_cnt <= 4'b0000;
	  
       end
     else
       begin
	  
         case (state[2:0])
         3'b000: begin // idle 
                   write_data_en <= 1'b0;
                   write_addr_en <= 1'b0;
                   if (WDF_ALMOST_FULL == 1'b0 && AF_ALMOST_FULL == 1'b0 && phy_init_initialization_done)

                     begin
                       state[2:0]       <= `write;
                       burst_count[2:0] <=  burst_len; // Burst length divided by 2
                     end
                   else 
                     begin
                       state[2:0]       <= `idle;
                       burst_count[2:0] <= 3'b000;
                     end
                 end
         3'b001: begin // write
                   if (WDF_ALMOST_FULL == 1'b0 && AF_ALMOST_FULL == 1'b0)

                     begin 
                       
		       if(state_cnt == 4'd8)
		       begin
			 state <= `read;
			 state_cnt <= 4'd0;
                         write_data_en    <= 1'b0;			  
		       end
		       else
		       begin
                         state[2:0]       <= `write;
			 write_data_en    <= 1'b1;
		       end
                       if (burst_count[2:0] != 3'b000)
                         burst_count[2:0] <= burst_count[2:0] - 1'b1;
                       else
                         burst_count[2:0] <=  burst_len - 1'b1;
                       if (burst_count[2:0] == 3'b001)
		       begin
                         write_addr_en  <= 1'b1;
			 state_cnt <= state_cnt + 1'b1;
		       end	
                       else
                         write_addr_en  <= 1'b0;
                     end
                   else
                     begin
                       state[2:0]       <= `idle;
                       write_addr_en    <= 1'b0;
                       write_data_en    <= 1'b0;
                       burst_count[2:0] <= 3'b000;
                     end                
         end // case: 3'b001
         3'b010: begin // read
	               
	    if ( AF_ALMOST_FULL == 1'b0) begin

		       if(state_cnt == 4'd8)
		       begin
			 write_addr_en  <= 1'b0;
			 if (WDF_ALMOST_FULL == 1'b0)
			 begin
			    write_data_en    <= 1'b1;
			    state_cnt <= 4'd0;
			    state <= `write;
			 end
		       end 
		       else
		       begin
                         state[2:0]       <= `read;
			 write_addr_en  <= 1'b1;
			 write_data_en    <= 1'b0;
			 state_cnt <= state_cnt + 1; 
		       end // else: !if(state_cnt == 4'd7)
	         end
	      else       
	            begin
                         state[2:0]       <= `idle;
			 write_addr_en  <= 1'b0;
			 write_data_en    <= 1'b0;
			  
	           end 
        
	    
         end // case: 3'b001  
	   
         default: begin
                    write_data_en <= 1'b0;          
                    write_addr_en <= 1'b0;          
                    state[2:0]    <= `idle;   
                  end
         endcase
       end  
   end 
   
   mem_test_cmp cmp_rd_data_00 (
                             .CLK(CLK),
	                     .RESET(RESET),
			     .test_cmp(test_cmp),
	                     .READ_DATA_VALID(READ_DATA_VALID),  
	                     .APP_COMPARE_DATA(app_cmp_data), 
	                     .READ_DATA_FIFO_OUT(READ_DATA_FIFO_OUT),  
	                     .ERROR(ERROR) 
                             );

   mem_test_rom backend_rom_00 (
                             .clk0(CLK),
                             .rst(RESET),
                             .bkend_data_en(write_data_en),
                             .bkend_wraddr_en(write_addr_en),
                             .bkend_rd_data_valid(READ_DATA_VALID),
                             .app_af_addr(APP_AF_ADDR), 
                             .app_af_WrEn(APP_AF_WREN),
                             .app_Wdf_data(APP_WDF_DATA),
                             .app_mask_data(APP_MASK_DATA),
                             .app_compare_data(app_cmp_data),
                             .app_Wdf_WrEn(APP_WDF_WREN)
                             );


endmodule