mem_clk_rst.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

module mem_clk_rst (  
input        SYS_CLK_N,
input        SYS_CLK_P,
input        CLK200_N,
input        CLK200_P,
input        SYS_RESET_IN,
             

output     CLK,
output     CLK90,
output     CLK200,
output     reg sys_rst,
output     reg sys_rst90,
output     reg sys_rst200,
output  [`clk_width-1:0]   DDR2_CK,
output  [`clk_width-1:0]   DDR2_CK_N

                   );
                   


wire [`clk_width-1:0]DDR2_CK_q;
wire [`clk_width-1:0]DDR2_CK_N_q;

wire       vcc;
wire       gnd;


assign vcc         = 1'b1;
assign gnd         = 1'b0;


wire       clk0_bufg_in;
wire       clk90_bufg_in;
wire       clkfb_bufg_in;
wire       clk0_bufg_out;
wire       clk90_bufg_out;
wire       clkdv_bufg_out;
wire       clk0_bufg1_out;
wire       clkfb_bufg_out;


reg           sys_rst_0;
reg           sys_rst_1;
reg           sys_rst_2;

reg           sys_rst90_0;
reg           sys_rst90_1;
reg           sys_rst90_2;


reg           sys_rst_200_0;
reg           sys_rst_200_1;
reg           sys_rst_200_2;

wire REF_CLK200_IN;
wire SYS_CLK_IN;
wire SYS_RESET;

assign CLK         = clk0_bufg_out;
assign CLK90       = clk90_bufg_out;
assign CLK200      = clk0_bufg1_out;
//assign CLK50       = clk50_bufg_out;

wire LOCKED;


assign SYS_RESET         = ~SYS_RESET_IN;

IBUFGDS_LVPECL_25  lvds_sys_clk_input ( 
                                       .I (SYS_CLK_P),      
                                       .IB(SYS_CLK_N),     
                                       .O (SYS_CLK_IN)
                                       );
                                      
IBUFGDS_LVPECL_25 lvpecl_clk200_in (
                                    .O(REF_CLK200_IN), 
                                    .I(CLK200_P), 
                                    .IB(CLK200_N)
                                    );               




defparam DCM_BASE0.DLL_FREQUENCY_MODE = "HIGH";
defparam DCM_BASE0.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_BASE0.CLKDV_DIVIDE = 16.0;
defparam DCM_BASE0.CLKFX_MULTIPLY = 2;
defparam DCM_BASE0.CLKFX_DIVIDE = 8;
defparam DCM_BASE0.FACTORY_JF = 16'hF0F0;





DCM_BASE DCM_BASE0 (
	            .CLK0(clk0_bufg_in),
	            .CLK180(),
	            .CLK270(),
	            .CLK2X(),
	            .CLK2X180(),
	            .CLK90(clk90_bufg_in),
	            .CLKDV(),
	            .CLKFX(),
	            .CLKFX180(),
	            .LOCKED(LOCKED),
	            .CLKFB(clk0_bufg_out),
	            .CLKIN(SYS_CLK_IN),
	            .RST(SYS_RESET)
                    );



                  
BUFG dcm_clk0 (
               .O(clk0_bufg_out),
               .I(clk0_bufg_in)
               );
                   
BUFG dcm_clk90 (
                .O(clk90_bufg_out),
                .I(clk90_bufg_in)
                );
                   

                
/*BUFG dcm_clkfx (
                .O(clkfg_bufg_out),
                .I(clkfg_bufg_in)
                );*/                
                
BUFG dcm1_clk0 (
                .O(clk0_bufg1_out),
                .I(REF_CLK200_IN)
                );                                  


always @ (posedge CLK)
begin
  if ( (LOCKED == 1'b0))
    begin
      sys_rst_0 <= 1'b1;
      sys_rst_1 <= 1'b1;
      sys_rst_2 <= 1'b1;
      sys_rst   <= 1'b1;
    end
  else
    begin
      sys_rst_0 <= 1'b0;
      sys_rst_1 <= sys_rst_0;
      sys_rst_2 <= sys_rst_1;
      sys_rst   <= sys_rst_2;
    end
end

always @ (posedge CLK90)
begin
  if ( (LOCKED == 1'b0))
    begin
      sys_rst90_0 <= 1'b1;
      sys_rst90_1 <= 1'b1;
      sys_rst90_2 <= 1'b1;
      sys_rst90 <= 1'b1;
    end
  else
    begin
      sys_rst90_0 <= 1'b0;
      sys_rst90_1 <= sys_rst90_0;
      sys_rst90_2 <= sys_rst90_1;
      sys_rst90   <= sys_rst90_2;
    end
end

always @ (posedge CLK200)
begin
  if ((LOCKED == 1'b0))
    begin
      sys_rst_200_0 <= 1'b1;
      sys_rst_200_1 <= 1'b1;
      sys_rst_200_2 <= 1'b1;
      sys_rst200   <= 1'b1;
    end
  else
    begin
      sys_rst_200_0 <= 1'b0;
      sys_rst_200_1 <= sys_rst_200_0;
      sys_rst_200_2 <= sys_rst_200_1;
      sys_rst200   <= sys_rst_200_2;
    end
end

defparam oddr_clk0.SRTYPE = "SYNC";
defparam oddr_clk0.DDR_CLK_EDGE = "OPPOSITE_EDGE";


ODDR oddr_clk0 (
                .Q(DDR2_CK_q[0]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
                );



defparam oddr_clk1.SRTYPE = "SYNC";
defparam oddr_clk1.DDR_CLK_EDGE = "OPPOSITE_EDGE";

ODDR oddr_clk1 (
                .Q(DDR2_CK_q[1]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
                );

defparam oddr_clk2.SRTYPE = "SYNC";
defparam oddr_clk2.DDR_CLK_EDGE = "OPPOSITE_EDGE";

ODDR oddr_clk2 (
                .Q(DDR2_CK_q[2]),
                .C(CLK),
                .CE(vcc),
                .D1(gnd),
                .D2(vcc),
                .R(gnd),
                .S(gnd)
                );


OBUFDS OBUFDS0
        (
         .I(DDR2_CK_q[0]),
         .O(DDR2_CK[0]),
         .OB(DDR2_CK_N[0])
         );

OBUFDS OBUFDS1
        (
         .I(DDR2_CK_q[1]),
         .O(DDR2_CK[1]),
         .OB(DDR2_CK_N[1])
         );
         
OBUFDS OBUFDS2
        (
         .I(DDR2_CK_q[2]),
         .O(DDR2_CK[2]),
         .OB(DDR2_CK_N[2])
         );

   
endmodule