qvgatiming.v

QVGA的Timing verilog 描述

`timescale      1ns/10ps

module  qvgatiming (
    clk1_3,
    rstn,
    
    sync_de,
    
    hsync,
    vsync,
    desync,
    
    rout,
    gout,
    bout,
    
    clkout,
    //bug
    pixcnt,
    linecnt  
);

parameter   HTOTAL  =   9'd408; 
parameter   HSYNC   =   9'd1;
parameter   HSIZE   =   9'd320;
parameter   HSTART  =   9'd70;
parameter   HEND    =   9'd390;

parameter   VTOTAL  =   9'd263;
parameter   VSYNC   =   9'd1;
parameter   VSIZE   =   9'd240;
parameter   VSTART  =   9'd13;
parameter   VEND    =   9'd253;

input           clk1_3;
input           rstn;
input           sync_de;

output          hsync;
output          vsync;
output          desync;
output      [8:0]   pixcnt;
output      [8:0]   linecnt;

output  [7:0]   rout;
output  [7:0]   gout;
output  [7:0]   bout;

output          clkout;

reg     [8:0]   pixcnt;
reg     [8:0]   linecnt;

reg     [7:0]   rout;
reg     [7:0]   gout;
reg     [7:0]   bout;
reg     [3:0]   count;
reg             clkout;

wire            ihsync;
wire            ivsync;
wire            ihde;
wire            ivde;
wire            idesync;

always @(posedge clk1_3 or negedge rstn) begin
    if(~rstn)begin
        count <= 2'd0;
        clkout <= 2'd0;
end    
    else if (count == 2'd1)begin
        count <= 2'd0;
        clkout <= ~clkout;
    end
    else 
        count <= count+2'd1;
end
always @(posedge clk1_3 or negedge rstn) begin
    if(~rstn)
        pixcnt <=#1 9'd1;
    else if (pixcnt == HTOTAL) 
        pixcnt <=#1 9'd1;
    else 
        pixcnt <=#1 (pixcnt + 1'b1);
end

assign  ihsync = (pixcnt <= HSYNC) ? 1'b0 : 1'b1;   
assign  ihde = ((pixcnt > HSTART) && (pixcnt <= HEND)) ? 1'b1 : 1'b0; 

always @(posedge clk1_3 or negedge rstn) begin
    if(~rstn)
        linecnt <= 9'd1;
    else if (linecnt == VTOTAL)
        linecnt <= 9'd1;
    else if (pixcnt == HTOTAL)
        linecnt <= linecnt + 1'b1;
    else
        linecnt <= linecnt;
end

assign  ivsync =  (linecnt <= VSYNC) ? 1'b0 : 1'b1;                       
assign  ivde = ((linecnt > VSTART) && (linecnt <= VEND)) ? 1'b1 : 1'b0;

assign  idesync = ivde & ihde; 

assign  desync = (sync_de == 1'b0) ? idesync : 1'b0;
assign  hsync  = (sync_de == 1'b1) ? ihsync : 1'b1;
assign  vsync  = (sync_de == 1'b1) ? ivsync : 1'b1;

//
// Horizontal Gray Level: 256
//

assign  grayprwindow = ((pixcnt >=  9'd71) && (pixcnt <  9'd76)) && idesync;
assign  graytopwindow = ((linecnt >=  9'd13) && (linecnt <  9'd18)) && idesync;
assign  grayprewindow = ((pixcnt >=  9'd76) && (pixcnt <=  9'd102)) && idesync;
assign  graycenwindow = ((pixcnt > 9'd102) && (pixcnt < 9'd358)) && idesync;
assign  grayposwindow = ((pixcnt >= 9'd357) && (pixcnt < 9'd385)) && idesync;
assign  graypowindow = ((pixcnt >= 9'd385) && (pixcnt <= 9'd390)) && idesync;
assign  graybotwindow = ((linecnt >= 9'd248) && (linecnt < 9'd253)) && idesync;


always @(*) 
    if(grayprwindow) begin
        rout = 8'h08;
        gout = 8'h02;
        bout = 8'hFF;
    end else if(graytopwindow) begin
        rout = 8'h08;
        gout = 8'h02;
        bout = 8'hFF;
    end else if(graybotwindow) begin
        rout = 8'h08;
        gout = 8'h02;
        bout = 8'hFF; 
    end else if(grayprewindow) begin
        rout = 8'h00;
        gout = 8'h00;
        bout = 8'h00;    
    end else if (graycenwindow) begin
        rout = pixcnt - 9'd103;
        gout = pixcnt - 9'd103;
        bout = pixcnt - 9'd103;
    end else if (grayposwindow) begin
        rout = 8'hff;
        gout = 8'hff;
        bout = 8'hff;
    end else if(graypowindow) begin
        rout = 8'h08;
        gout = 8'h02;
        bout = 8'hFF;
                    
    end else begin    
        rout = 8'h00;
        gout = 8'h00;
        bout = 8'h00;
    end
       
    
endmodule