📄 chengfaqi.rpt
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Project Information f:\shiweichenfaqi\chengfaqi.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 12/20/2006 20:25:40
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
chengfaqi
EPM7096LC68-7 12 7 0 85 45 88 %
chengfaqi1
EPM7032LC44-6 9 6 0 10 5 31 %
TOTAL: 21 13 0 95 50 74 %
User Pins: 9 10 0
Project Information f:\shiweichenfaqi\chengfaqi.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'Y8' is stuck at GND
Info: Trying to find new partition/fit after discarding assignments as requested with the Partitioner/Fitter Status dialog box
Project Information f:\shiweichenfaqi\chengfaqi.rpt
** MULTIPLE PIN CONNECTIONS **
For node name 'SEL'
Connect: {chengfaqi1@5, chengfaqi@23}
For node name 'M4'
Connect: {chengfaqi@9, chengfaqi1@4}
For node name 'M3'
Connect: {chengfaqi@10, chengfaqi1@8}
For node name 'M2'
Connect: {chengfaqi@12, chengfaqi1@7}
For node name 'M1'
Connect: {chengfaqi@13, chengfaqi1@6}
For node name 'N4'
Connect: {chengfaqi@33, chengfaqi1@9}
For node name 'N3'
Connect: {chengfaqi@5, chengfaqi1@11}
For node name 'N2'
Connect: {chengfaqi@7, chengfaqi1@12}
For node name 'N1'
Connect: {chengfaqi@8, chengfaqi1@13}
Connect: {chengfaqi1@32,chengfaqi@19}
Connect: {chengfaqi1@33,chengfaqi@20}
Connect: {chengfaqi1@34,chengfaqi@22}
Project Information f:\shiweichenfaqi\chengfaqi.rpt
** FILE HIERARCHY **
|shiweichefa:1|
|shiweichefa:1|7weijiafai:1|
|shiweichefa:1|7weijiafai:1|quanjiaqi:1|
|shiweichefa:1|7weijiafai:1|quanjiaqi:1|7486:1|
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|shiweichefa:1|6weijiafai:2|quanjiaqi:6|7486:1|
|shiweichefa:1|6weijiafai:2|quanjiaqi:6|7486:4|
|shiweichefa:1|6weijiafai:2|quanjiaqi:5|
|shiweichefa:1|6weijiafai:2|quanjiaqi:5|7486:1|
|shiweichefa:1|6weijiafai:2|quanjiaqi:5|7486:4|
|shiweichefa:1|6weijiafai:2|quanjiaqi:4|
|shiweichefa:1|6weijiafai:2|quanjiaqi:4|7486:1|
|shiweichefa:1|6weijiafai:2|quanjiaqi:4|7486:4|
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|shiweichefa:1|6weijiafai:2|quanjiaqi:3|7486:1|
|shiweichefa:1|6weijiafai:2|quanjiaqi:3|7486:4|
|shiweichefa:1|6weijiafai:2|quanjiaqi:2|
|shiweichefa:1|6weijiafai:2|quanjiaqi:2|7486:1|
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|shiweichefa:1|5weijiafai:3|
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|shiweichefa:1|5weijiafai:3|quanjiaqi:1|7486:1|
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|shiweichefa:1|5weijiafai:3|quanjiaqi:5|7486:1|
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|shiweichefa:1|5weijiafai:3|quanjiaqi:4|7486:4|
|shiweichefa:1|5weijiafai:3|quanjiaqi:3|
|shiweichefa:1|5weijiafai:3|quanjiaqi:3|7486:1|
|shiweichefa:1|5weijiafai:3|quanjiaqi:3|7486:4|
|shiweichefa:1|5weijiafai:3|quanjiaqi:2|
|shiweichefa:1|5weijiafai:3|quanjiaqi:2|7486:1|
|shiweichefa:1|5weijiafai:3|quanjiaqi:2|7486:4|
|shumazhuanhuan:2|
|shumazhuanhuan:3|
|74157:5|
|74157:6|
Device-Specific Information: f:\shiweichenfaqi\chengfaqi.rpt
chengfaqi
***** Logic for device 'chengfaqi' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R R
E E E E E
S V S S S S
E C E E V E E
R C R R C R R
G V I G G G G G V V C V V
M N N N N E N N N N N N E E I E E
4 1 2 D 3 D T D D D D D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
M3 | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
M2 | 12 58 | GND
M1 | 13 57 | RESERVED
RESERVED | 14 56 | RESERVED
Y6 | 15 55 | RESERVED
GND | 16 54 | RESERVED
RESERVED | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | RESERVED
~PIN001 | 19 51 | RESERVED
~PIN002 | 20 50 | RESERVED
VCCIO | 21 49 | Y2
~PIN003 | 22 48 | GND
SEL | 23 47 | Y3
RESERVED | 24 46 | RESERVED
RESERVED | 25 45 | RESERVED
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
R R R R V R N G V R Y G Y Y Y R V
E E E E C E 4 N C E 7 N 5 4 1 E C
S S S S C S D C S D S C
E E E E I E I E E I
R R R R O R N R R O
V V V V V T V V
E E E E E E E
D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: f:\shiweichenfaqi\chengfaqi.rpt
chengfaqi
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 7/ 8( 87%) 16/16(100%) 32/36( 88%)
B: LC17 - LC32 15/16( 93%) 5/ 8( 62%) 16/16(100%) 20/36( 55%)
C: LC33 - LC48 16/16(100%) 1/ 8( 12%) 15/16( 93%) 28/36( 77%)
D: LC49 - LC64 15/16( 93%) 4/ 8( 50%) 16/16(100%) 30/36( 83%)
E: LC65 - LC80 16/16(100%) 2/ 8( 25%) 16/16(100%) 25/36( 69%)
F: LC81 - LC96 15/16( 93%) 0/ 8( 0%) 16/16(100%) 29/36( 80%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 19/48 ( 39%)
Total logic cells used: 85/96 ( 88%)
Total shareable expanders used: 45/96 ( 46%)
Total Turbo logic cells used: 85/96 ( 88%)
Total shareable expanders not available (n/a): 50/96 ( 52%)
Average fan-in: 9.41
Total fan-in: 800
Total input pins required: 12
Total output pins required: 7
Total bidirectional pins required: 0
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