cntm16.vhd

来自「DDS直接数字频率合成器」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cntm16 is
  port(
       clk:in bit;
         oc:inout integer range 0 to 15
); 
end;

architecture a of cntm16 is
begin
 process(clk)
begin
 if(clk'event and clk='1') then
oc<=oc+1;
end if;
end process;
end ;