fd_dmc.vhd

来自「DDS直接数字频率合成器」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity  fd_dmc is
  port(clk,key:in std_logic;
       cpo:out std_logic
); 
end ;

architecture a of fd_dmc is
signal cp:std_logic;
signal jsp:integer range 0 to 3;

begin 
  process(clk)
    begin
if(clk'event and clk='1') then
    if key='1' then 
 
      if jsp=3 then
      jsp<=jsp;
      else
        jsp<=jsp+1;
      end if;

      if jsp=1 then
        cp<='1';
      else
        cp<='0';
      end if;
    else jsp<=0;
end if;
end if;
cpo<=cp;
end process;
end ;