adder.vhd

来自「DDS直接数字频率合成器」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity  adder is
  port(
       op:in std_logic_vector(9 downto 0);
        k:in std_logic_vector(3 downto 0);
   result:out std_logic_vector(9 downto 0)); 
end adder;

architecture maxpld of adder is
begin 
  result<=op+('0'&k);
end maxpld;