onemux3.vhd

来自「DDS直接数字频率合成器」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity onemux3 is
  port(
       s:in integer range 0 to 2;
     ms:out integer range 0 to 7          
        ); 
end;

architecture a of onemux3 is
begin
 process(s)
begin
 if(s=0) then
ms<=4;
elsif(s=1) then
ms<=2;
elsif(s=2) then
ms<=1;
end if;
end process;
end;