allnot.vhd

来自「DDS直接数字频率合成器」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity  allnot is
  port(d:in std_logic_vector(7 downto 0);
       y:out std_logic_vector(7 downto 0)
); 
end allnot;

architecture a of allnot is
begin 
  process(d)
    begin
y<=(not d);
end process;
end a;