fourmux3.vhd

来自「DDS直接数字频率合成器」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fourmux3 is
  port(
       s:in integer range 0 to 2;
      a,b,c:in integer range 0 to 15;          
         fout:out integer range 0 to 15
); 
end;

architecture a of fourmux3 is
begin
 process(s)
begin
 if(s=0) then
fout<=a;
elsif(s=1) then
fout<=b;
elsif(s=2) then
fout<=c;
end if;
end process;
end;