compare3_tb.v

来自「PacoBlaze is a from-scratch synthesizabl」· Verilog 代码 · 共 122 行

/*
	Compare KCPSM3 and PacoBlaze3
*/

`define PACOBLAZE3
`define TEST_FILE "../test/pb3_test.rmh"

`include "timescale_inc.v"
`include "pacoblaze_inc.v"

module compare3_tb;

parameter tck = 10, program_cycles = 100;

defparam glbl.ROC_WIDTH = 0;

reg clk, rst, ir; // clock, reset, interrupt req
wire [`code_depth-1:0] ad_0, ad_1; // instruction address
reg [`operand_width-1:0] prt_0[0:`port_size-1], prt_1[0:`port_size-1];
wire [`operand_width-1:0] pa_0, pa_1, po_0, po_1; // port id, port out
wire rd_0, rd_1, wr_0, wr_1, ia_0, ia_1; // read strobe, write strobe, interrupt ack

wire [`code_width-1:0] di_0, di_1;
wire [`operand_width-1:0] pi_0 = prt_0[pa_0], pi_1 = prt_1[pa_1]; // port in

/* PacoBlaze program memory */
blockram #(.width(`code_width),.depth(`code_depth)) rom_0(
	.clk(clk),
	.rst(rst),
	.en(1),
	.we(0),
	.ad(ad_0),
	.di(0),
	.do(di_0)
);

/* PacoBlaze dut */
pacoblaze3 dut_0(
	.clk(clk),
	.reset(rst),
	.address(ad_0),
	.instruction(di_0),
	.port_id(pa_0),
	.read_strobe(rd_0),
	.write_strobe(wr_0),
	.in_port(pi_0),
	.out_port(po_0),
	.interrupt(ir),
	.interrupt_ack(ia_0)
);

/* KCPSM3 program memory */
blockram #(.width(`code_width),.depth(`code_depth)) rom_1(
	.clk(clk),
	.rst(rst),
	.en(1),
	.we(0),
	.ad(ad_1),
	.di(0),
	.do(di_1)
);

/* KCPSM3 dut */
kcpsm3 dut_1(
	.clk(clk),
	.reset(rst),
	.address(ad_1),
	.instruction(di_1),
	.port_id(pa_1),
	.read_strobe(rd_1),
	.write_strobe(wr_1),
	.in_port(pi_1),
	.out_port(po_1),
	.interrupt(ir),
	.interrupt_ack(ia_1)
);

/* Clocking device */
always #(tck/2) clk = ~clk;

/* Watch external ports */
always @(posedge clk)	begin
	if (wr_0) prt_0[pa_0] <= po_0;
	if (wr_1) prt_1[pa_1] <= po_1;
end

always @(negedge clk) begin
	$display("%h:%h %h:%h", ad_0, di_0, ad_1, di_1);
	if (ad_0 != ad_1) $display("***address mismatch***");
end

/* Simulation setup */
initial begin
	$dumpvars(-1, compare3_tb);
	$dumpfile("compare3_tb.vcd");
	$readmemh(`TEST_FILE, rom_0.ram);
	$readmemh(`TEST_FILE, rom_1.ram);
end

/* Simulation */
integer i;
initial begin
	/* Initialize port memory */
	for (i=0; i<`port_size; i=i+1) begin
		prt_0[i] = i;
		prt_1[i] = i;
	end

	clk = 0; rst = 1; ir = 0;
	#(tck*3);
	@(negedge clk) rst = 0; // free processor

	#(tck*50);
	@(negedge clk) ir = 1; // flag interrupt
	@(negedge clk) ;
	@(negedge clk) ir = 0;

	#(program_cycles*tck+100) $finish;
end

endmodule