m_keyscan.v

一个用verilog语言实现的包含：键盘扫描

//  author: Dandy Nee
//  mail:   [e-mail]
//  module: HW KeyScan Module
//  version:0.1
//  **************************
//  all functions are provided as if okay
//  run at your own risk
//  **************************
//
//  problem:    there is one keyvalue valid 
//              indicator signal needed
//
//------------------------------------------------

//
//         ^  ^  ^  ^ Pull Up
//         |  |  |  |
//  x0  >--|--|--|--|-
//  x1  >--|--|--|--|-
//  x2  >--|--|--|--|-
//  x3  >--|--|--|--|-
//  y0  <--+  |  |  |
//  y1  <-----+  |  |
//  y2  <--------+  |
//  y3  <-----------+
//
module  m_keyscan(
            clk,        //system clk
            rstb,       //system a-rst, low active
            //
            clkdiv,     //clock divide coef
            //
            keyvalue,   //returned key
            //
            x,          //x-row scan out
            y           //y-col scan in
            );

input       clk, rstb;
input   [19:0]  clkdiv;
output  [15:0]  keyvalue;
output  [3:0]   x;
input   [3:0]   y;


reg [19:0]  cnt;
always  @(posedge clk or negedge rstb)
if(~rstb)
    cnt<=0;
else
    cnt <= cnt==clkdiv ? 0 : cnt+1;

reg clken;
always  @(posedge clk or negedge rstb)
if(~rstb)
    clken <= 0;
else
    clken <= cnt==clkdiv;

reg [2:0]   fsm;
always  @(posedge clk or negedge rstb)
if(~rstb)
    fsm <= 0;
else if(clken)
    fsm <= fsm+1;   //8 states

reg [15:0]  keyvalue;
reg [3:0]   x;
always  @(posedge clk or negedge rstb)
if(~rstb)
    keyvalue <= 0;
else if(clken)
    case(fsm)
    0:  begin
        x <= 4'b1110;
        end
    1:  begin
        keyvalue[3:0] <= ~y;
        end
    2:  begin
        x <= 4'b1101;
        end
    3:  begin
        keyvalue[7:4] <= ~y;
        end
    4:  begin
        x <= 4'b1011;
        end
    5:  begin
        keyvalue[11:8] <= ~y;
        end
    6:  begin
        x <= 4'b0111;
        end
    7:  begin
        keyvalue[15:12] <= ~y;
        end
    endcase

endmodule