m_vgaball.v

一个用verilog语言实现的包含：键盘扫描

//
//  Vga Ball Bounce Demo For FPGAKIT
//  All Rights Reserved By Viputech
//          [e-mail]
//
`define VGA 1
module m_vgabll(
            clk,
            rstb,
            //vga inf
            r_dac,
            g_dac,
            b_dac,
            hs_dac,
            vs_dac,
            enb_dac,
            pclk_dac,
            //
            led,
            //
            xrow,
            ycol
            );
input       clk, rstb;
//vga inf
output  [4:0]   r_dac;
output  [5:0]   g_dac;
output  [4:0]   b_dac;
output          hs_dac,
                vs_dac,
                enb_dac,
                pclk_dac;
output  [3:0]   led;
output  [3:0]   xrow;
input   [3:0]   ycol;

`ifdef VGA
parameter   HP = 800,
            VP = 525,
            HS1 = 659,
            HS2 = 755,
            VS0 = 699,
            VS1 = 493,
            VS2 = 494,
            HE = 639,
            VE = 479;
`else
parameter   HP = 200,
            VP = 60,
            HS1 = 170,
            HS2 = 180,
            VS0 = 175,
            VS1 = 50,
            VS2 = 51,
            HE = 159,
            VE = 40;
`endif

wire    [15:0]  keyvalue;

reg [9:0]   hcnt_r, vcnt_r;
reg hs_dac, vs_dac, enb_dac;
//  Horiz_sync  ------------------------------------__________--------
//  H_count       0                640             659       755    799
//  Vert_sync   -----------------------------------------------_______------------
//  V_count      0                                      480    493-494          524

always  @(posedge clk or negedge rstb)
if(~rstb)
    hcnt_r <= 0;
else
    hcnt_r <= hcnt_r == HP-1 ? 0 : hcnt_r+1;

always  @(posedge clk or negedge rstb)
if(~rstb)
    vcnt_r <= 0;
else if(hcnt_r==VS0)
    vcnt_r <= vcnt_r == VP-1 ? 0 : vcnt_r+1;

always  @(posedge clk or negedge rstb)
if(~rstb)
    hs_dac <= 1;
else if(hcnt_r>=HS1 && hcnt_r<=HS2)
    hs_dac <= 0;
else
    hs_dac <= 1;

always  @(posedge clk or negedge rstb)
if(~rstb)
    vs_dac <= 1;
else if(vcnt_r == VS1 || vcnt_r == VS2)
    vs_dac <= 0;
else
    vs_dac <= 1;

wire    video_on;
assign  video_on = vcnt_r<=VE && hcnt_r<=HE;

reg [9:0]   ball_x, ball_y;
/*
//if you want to try self bouncing, use this 
reg x_dir, y_dir;
always  @(posedge clk or negedge rstb)
if(~rstb)
    begin
    ball_x <= 10;
    ball_y <= 10;
    x_dir <= 1;
    y_dir <= 1;
    end
else if(vcnt_r==VP-1 && hcnt_r==VS0)
    begin
    ball_x <= x_dir ? ball_x+1 : ball_x-1;
    ball_y <= y_dir ? ball_y+1 : ball_y-1;
    
    if(x_dir && ball_x==HE-10) x_dir <= 0;
    else if(!x_dir && ball_x==10) x_dir <= 1;
    
    if(y_dir && ball_y==VE-10) y_dir <= 0;
    else if(!y_dir && ball_y==10) y_dir <= 1;
    end
*/

always  @(posedge clk or negedge rstb)
if(~rstb)
    begin
    ball_x <= 310;
    ball_y <= 230;
    end
else if(vcnt_r==VP-1 && hcnt_r==VS0)
    begin
    if(keyvalue==16'h0020)
        ball_x <= 310;
    else if(((keyvalue==16'h0010) || (keyvalue==16'h0001) || (keyvalue==16'h0100)) && (ball_x>10))
        ball_x <= ball_x-1;
    else if(((keyvalue==16'h0040) || (keyvalue==16'h0004) || (keyvalue==16'h0400)) && (ball_x<629))
        ball_x <= ball_x+1;
    
    if(keyvalue==16'h0020)
        ball_y <= 230;
    else if(((keyvalue==16'h0002)  || (keyvalue==16'h0001) || (keyvalue==16'h0004))&& (ball_y>10))
        ball_y <= ball_y-1;
    else if(((keyvalue==16'h0200) || (keyvalue==16'h0100) || (keyvalue==16'h0400))&& (ball_y<469))
        ball_y <= ball_y+1;
    end


wire    ball_on;
assign  ball_on = vcnt_r>=(ball_y-10) && vcnt_r<=(ball_y+10) && hcnt_r>=(ball_x-10) && hcnt_r<=(ball_x+10);

reg [15:0]  pix_data;
always  @(posedge clk or negedge rstb)
if(~rstb)
    pix_data <= 0;
else
    pix_data <= video_on ? (ball_on ? 16'b11111_000000_00000
                                    : vcnt_r<VE/4 ? 16'b10000_100000_00000
                                    : vcnt_r<VE/2 ? 16'b11000_110000_01000
                                    : vcnt_r<VE*3/4 ? 16'b11100_111000_01100
                                    : 16'b11110_111100_01110)
                         : 16'h0;

assign  {r_dac, g_dac, b_dac} = pix_data;

always  @(posedge clk or negedge rstb)
if(~rstb)
    enb_dac <= 0;
else
    enb_dac <= video_on;

assign  pclk_dac = ~clk;
//---------------------
m_key_led
    u_key_led(
            .clk        (clk),
            .rstb       (rstb),
            //led
            .led        (led),
            //key
            .xrow       (xrow),
            .ycol       (ycol),
            //
            .keyvalue   (keyvalue)
            );
endmodule