shiftreg_2.vhd

来自「verilog实现shiftreg」· VHDL 代码 · 共 26 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY shiftreg IS
	PORT(Di,clk		 : IN	STD_LOGIC;
		 Q3,Q2,Q1,Q0 : OUT	STD_LOGIC);
END shiftreg;

ARCHITECTURE a OF shiftreg IS
BEGIN
 PROCESS (clk)
 VARIABLE temp :  STD_LOGIC_VECTOR(3 DOWNTO 0);
 BEGIN
	IF (clk'event and clk = '1') THEN
          temp(0) := temp(1);
          temp(1) := temp(2);    
          temp(2) := temp(3);
          temp(3) := Di;
    END IF;
    Q3 <= temp(3); Q2 <= temp(2); Q1 <= temp(1); Q0 <= temp(0); 
 END PROCESS;
END a;